Zexue Liu
Orcid: 0000-0002-7333-3119Affiliations:
- Peking University, Beijing, China
According to our database1,
Zexue Liu
authored at least 21 papers
between 2017 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Using scaffolding theory in serious games to enhance traditional Chinese murals culture learning.
Comput. Animat. Virtual Worlds, 2024
How generous interface affect user experience and behavior: Evaluating the information display interface for museum cultural heritage.
Comput. Animat. Virtual Worlds, 2024
2023
A 2.85-mm<sup>2</sup> Wideband RF Transceiver in 40-nm CMOS for IoT Micro-Hub Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., October, 2023
The influence of art programming courses on design thinking and computational thinking in college art and design students.
Educ. Inf. Technol., September, 2023
2022
Traditional Mural Learning Effectiveness of Using Serious Game Based on Scaffolding Teaching Theory.
Proceedings of the HCI International 2022 Posters, 2022
Proceedings of the HCI International 2022 Posters, 2022
2021
A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A Gm-Compensated 46-101 GHz Broadband Power Amplifier for High-Resolution FMCW Radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A 0.5-V 3.69-nW Complementary Source-Follower-C Based Low-Pass Filter for Wearable Biomedical Applications.
IEEE Trans. Circuits Syst., 2020
An 81-99 GHz Tripler with Fundamental Cancellation and 3rd Harmonic Enhancement Technique in 40-nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
2019
A 2.9 GHz Variable Inductor-Based DCO With 1.3 kHz Frequency Resolution for FMCW Radar Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A 28 GHz 8-Bit Calibration-Free LO-Path Phase Shifter using Transformer-Based Vector Summing Topology in 40 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Calibration-Free Fractional-N ADPLL using Retiming Architecture and a 9-bit 0.3ps-INL Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
A 2.4-mW interference-resilient receiver front end with series N-path filter-based balun for body channel communication.
Int. J. Circuit Theory Appl., 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 12-bit 2.5 GHz 0.37ps-Peak-INL Digital-to-Time Converter with Parasitic-Insensitive Charge-Based Phase Interpolator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 43.2 μW 2.4 GHz 64-QAM Pseudo-Backscatter Modulator Based on Integrated Directional Coupler.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017