Zeshan Chishti

According to our database, Zeshan Chishti authored at least 37 papers between 2003 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

DaeMon: Architectural Support for Efficient Data Movement in Fully Disaggregated Systems.

Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar

Proc. ACM Meas. Anal. Comput. Syst., March, 2023

Architectural Support for Efficient Data Movement in Disaggregated Systems.

Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar

CoRR, 2023

DaeMon: Architectural Support for Efficient Data Movement in Disaggregated Systems.

Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar

CoRR, 2023

Architectural Support for Efficient Data Movement in Fully Disaggregated Systems.

Christina Giannoula, Kailong Huang, Jonathan Tang, Nectarios Koziris, Georgios I. Goumas, Zeshan Chishti, Nandita Vijaykumar

Proceedings of the Abstract Proceedings of the 2023 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2023

2021

Improving Streaming Graph Processing Performance using Input Knowledge.

Abanti Basak, Zheng Qu, Jilan Lin, Alaa R. Alameldeen, Zeshan Chishti, Yufei Ding, Yuan Xie

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

2020

SAGA-Bench: Software and Hardware Characterization of Streaming Graph Analytics Workloads.

Abanti Basak, Jilan Lin, Ryan Lorica, Xinfeng Xie, Zeshan Chishti, Alaa R. Alameldeen, Yuan Xie

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

ZCOMP: Reducing DNN Cross-Layer Memory Footprint Using Vector Extensions.

Berkin Akin, Zeshan A. Chishti, Alaa R. Alameldeen

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

Memory system characterization of deep learning workloads.

Zeshan Chishti, Berkin Akin

Proceedings of the International Symposium on Memory Systems, 2019

TicToc: Enabling Bandwidth-Efficient DRAM Caching for Both Hits and Misses in Hybrid Memory Systems.

Vinson Young, Zeshan A. Chishti, Moinuddin K. Qureshi

Proceedings of the 37th IEEE International Conference on Computer Design, 2019

2018

Reducing DRAM Refresh Overheads with Refresh-Access Parallelism.

Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu

CoRR, 2018

Flexible associativity for DRAM caches.

Elvira Teran, Zeshan Chishti, Zhe Wang, Chris Wilkerson, Daniel A. Jiménez

Proceedings of the 15th ACM International Conference on Computing Frontiers, 2018

2017

Improving DRAM Performance by Parallelizing Refreshes with Accesses.

Kevin K. Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu

CoRR, 2017

Hardware-Software Co-design to Mitigate DRAM Refresh Overheads: A Case for Refresh-Aware Process Scheduling.

Jagadish B. Kotra, Narges Shahidi, Zeshan A. Chishti, Mahmut T. Kandemir

Proceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems, 2017

2016

DRAM Refresh Mechanisms, Penalties, and Trade-Offs.

Ishwar Bhati, Mu-Tien Chang, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob

IEEE Trans. Computers, 2016

Reducing Performance Impact of DRAM Refresh by Parallelizing Refreshes with Accesses.

Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu

CoRR, 2016

Path confidence based lookahead prefetching.

Jinchun Kim, Seth H. Pugsley, Paul V. Gratz, A. L. Narasimha Reddy, Chris Wilkerson, Zeshan Chishti

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

The Case for Associative DRAM Caches.

Paul Tschirhart, Jim Stevens, Zeshan Chishti, Bruce L. Jacob

Proceedings of the Second International Symposium on Memory Systems, 2016

2015

Efficiently prefetching complex address patterns.

Manjunath Shevgoor, Sahil Koladiya, Rajeev Balasubramonian, Chris Wilkerson, Seth H. Pugsley, Zeshan Chishti

Proceedings of the 48th International Symposium on Microarchitecture, 2015

Bringing Modern Hierarchical Memory Systems Into Focus: A study of architecture and workload factors on system performance.

Paul Tschirhart, Jim Stevens, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob

Proceedings of the 2015 International Symposium on Memory Systems, 2015

Flexible auto-refresh: enabling scalable and energy-efficient DRAM refresh reductions.

Ishwar Bhati, Zeshan Chishti, Shih-Lien Lu, Bruce L. Jacob

Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

2014

Transparent Hardware Management of Stacked DRAM as Part of Memory.

Jaewoong Sim, Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Hyesoon Kim

Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

Sandbox Prefetching: Safe run-time evaluation of aggressive prefetchers.

Seth H. Pugsley, Zeshan Chishti, Chris Wilkerson, Peng-fei Chuang, Robert L. Scott, Aamer Jaleel, Shih-Lien Lu, Kingsum Chow, Rajeev Balasubramonian

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

Improving DRAM performance by parallelizing refreshes with accesses.

Kevin Kai-Wei Chang, Donghyuk Lee, Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Yoongu Kim, Onur Mutlu

Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013

Coordinated refresh: Energy efficient techniques for DRAM refresh scheduling.

Ishwar Bhati, Zeshan Chishti, Bruce L. Jacob

Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Operating SECDED-based caches at ultra-low voltage with FLAIR.

Moinuddin K. Qureshi, Zeshan Chishti

Proceedings of the 2013 43rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2013

2011

Adaptive Cache Design to Enable Reliable Low-Voltage Operation.

Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu

IEEE Trans. Computers, 2011

Energy-efficient cache design using variable-strength error-correcting codes.

Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu

Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

2010

Rank-aware cache replacement and write buffering to improve DRAM energy efficiency.

Ahmed M. Amin, Zeshan Chishti

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

Reducing cache power with low-cost, multi-bit error-correcting codes.

Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu

Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009

Trading Off Cache Capacity for Low-Voltage Operation.

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu

IEEE Micro, 2009

Improving cache lifetime reliability at ultra-low voltages.

Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu

Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

2008

Optimal Power/Performance Pipeline Depth for SMT in Scaled Technologies.

Zeshan Chishti, T. N. Vijaykumar

IEEE Trans. Computers, 2008

Shapeshifter: Dynamically changing pipeline width and speed to address process variations.

Eric Chun, Zeshan Chishti, T. N. Vijaykumar

Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Trading off Cache Capacity for Reliability to Enable Low Voltage Operation.

Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu

Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

2005

Optimizing Replication, Communication, and Capacity Allocation in CMPs.

Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar

Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005

2004

Wire Delay is Not a Problem for SMT (In the Near Future).

T. N. Vijaykumar, Zeshan Chishti

Proceedings of the 31st International Symposium on Computer Architecture (ISCA 2004), 2004

2003

Distance Associativity for High-Performance Energy-Efficient Non-Uniform Cache Architectures.

Zeshan Chishti, Michael D. Powell, T. N. Vijaykumar

Proceedings of the 36th Annual International Symposium on Microarchitecture, 2003