Zeljko Zilic

Orcid: 0000-0002-6887-3911

According to our database1, Zeljko Zilic authored at least 194 papers between 1993 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Systematic Review of IoT-Based Solutions for User Tracking: Towards Smarter Lifestyle, Wellness and Health Management.
Sensors, September, 2024

Sensing Data Concealment in NFTs: A Steganographic Model for Confidential Cross-Border Information Exchange.
Sensors, February, 2024

Optimizing Auditory Immersion Safety on Edge Devices: An On-Device Sound Event Detection System.
Proceedings of the Odyssey 2024: The Speaker and Language Recognition Workshop, 2024

Automated Assertion Checker Generator and Information Flow Tracking for Security Verification.
Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023
Scheduling Sparse LEO Satellite Transmissions for Remote Water Level Monitoring.
Sensors, 2023

Performance analysis of a private blockchain network built on Hyperledger Fabric for healthcare.
Inf. Process. Manag., 2023

An IoT Ecosystem Platform for the Evaluation of Blockchain Feasibility.
IEEE Internet Things J., 2023

Quality-driven Design Methodology for PUFs in FPGAs for Secure IoT.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

Non-Fungible Tokens (NFTs) as a Means for Blockchain Networks Integration in Healthcare.
Proceedings of the 5th Conference on Blockchain Research & Applications for Innovative Networks and Services, 2023

An Evaluation Framework for Assessing IPFS Performance within a Blockchain-Based Healthcare System.
Proceedings of the IEEE International Conference on Blockchain, 2023

2022
Wearable Vibrotactile System as an Assistive Technology Solution.
Mob. Networks Appl., 2022

A Strong Node Classification Baseline for Temporal Graphs.
Proceedings of the 2022 SIAM International Conference on Data Mining, 2022

Sleep Stage Detection on a Wearable Headband Using Deep Neural Networks.
Proceedings of the Internet of Things, 2022

A Stylized Presence Detection System in the Era of Blockchain and Big Data.
Proceedings of the IEEE International Conference on Big Data, 2022

Decentralized Storage for Big Data in Healthcare between Reality and Ambition: IPFS and Sia.
Proceedings of the IEEE International Conference on Big Data, 2022

A Technical Assessment of Blockchain in Healthcare with a Focus on Big Data.
Proceedings of the IEEE International Conference on Big Data, 2022

2021
A Multistage Blockchain-Based Secure and Trustworthy Smart Healthcare System Using ECG Characteristic.
IEEE Internet Things Mag., 2021

SigTran: Signature Vectors for Detecting Illicit Activities in Blockchain Transaction Networks.
Proceedings of the Advances in Knowledge Discovery and Data Mining, 2021

Making Case for Using RAFT in Healthcare Through Hyperledger Fabric.
Proceedings of the 2021 IEEE International Conference on Big Data (Big Data), 2021

2020
Energy and Task-Aware Partitioning on Single-ISA Clustered Heterogeneous Processors.
IEEE Trans. Parallel Distributed Syst., 2020

An Ultrasound-Based Biomedical System for Continuous Cardiopulmonary Monitoring: A Single Sensor for Multiple Information.
IEEE Trans. Biomed. Eng., 2020

A blockchain-based eHealthcare system interoperating with WBANs.
Future Gener. Comput. Syst., 2020

Lumen & Media Segmentation of IVUS Images via Ellipse Fitting Using a Wavelet-Decomposed Subband CNN.
Proceedings of the 30th IEEE International Workshop on Machine Learning for Signal Processing, 2020

Detecting Malicious Ethereum Entities via Application of Machine Learning Classification.
Proceedings of the 2nd Conference on Blockchain Research & Applications for Innovative Networks and Services, 2020

2019
A baseband processing ASIC for body area networks.
J. Ambient Intell. Humaniz. Comput., 2019

FoodTracker: A Real-time Food Detection Mobile Application by Deep Convolutional Neural Networks.
CoRR, 2019

Exploring Better Food Detection via Transfer Learning.
Proceedings of the 16th International Conference on Machine Vision Applications, 2019

A Structurally Regularized Convolutional Neural Network for Image Classification Using Wavelet-Based Subband Decomposition.
Proceedings of the 2019 IEEE International Conference on Image Processing, 2019

An Encryption Method for BAN Using the Channel Characteristics.
Proceedings of the Advances in Body Area Networks I, 2019

2018
A Software Defined Radio Evaluation Platform for WBAN Systems.
Sensors, 2018

Ultrasound Sensors for Diaphragm Motion Tracking: An Application in Non-Invasive Respiratory Monitoring.
Sensors, 2018

Protocol with self-adaptive GB for BANs.
IET Commun., 2018

A novel security scheme for Body Area Networks compatible with smart vehicles.
Comput. Networks, 2018

Multi-point Security by a Multiplatform-compatible Multifunctional Authentication and Encryption Board.
J. Comput. Inf. Technol., 2018

Using the Characteristic Value of the Body Channel for Encryption of Body Area Networks.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Area and Energy Efficient Magnetic Full Adder based on Differential Spin Hall MRAM.
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

An ASIC Implementation of Security Scheme for Body Area Networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

A Continuous Respiratory Monitoring System Using Ultrasound Piezo Transducer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Ultrasound Based Respiratory Monitoring Evaluation Under Human Body Motions.
Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

Implementation and Analysis of Spin-Torque-Based Reversible D-Latch.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018

Software Defined Radio-Based Testbed for Wireless Body Area Network.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018

2017
A Comprehensive Analysis on Wearable Acceleration Sensors in Human Activity Recognition.
Sensors, 2017

A Novel Algorithm to Reduce Machine Learning Efforts in Real-Time Sensor Data Analysis.
Proceedings of the Wireless Mobile Communication and Healthcare, 2017

Designing and Evaluating a Vibrotactile Language for Sensory Substitution Systems.
Proceedings of the Wireless Mobile Communication and Healthcare, 2017

Ultrasound sensors and its application in human heart rate monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Concealed regression for aggregation in low power wireless networks.
Proceedings of the 20th Conference on Innovations in Clouds, Internet and Networks, 2017

Evaluation of an RF wearable device for non-invasive real-time hydration monitoring.
Proceedings of the 14th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2017

2016
Respiration Disorders Classification With Informative Features for m-Health Applications.
IEEE J. Biomed. Health Informatics, 2016

Adaptive parametric tuning of glucose-insulin kinetics models using multilayer perceptrons.
Proceedings of the Summer Computer Simulation Conference, 2016

Design of a modeling and validation platform for closed loop glucose control.
Proceedings of the Summer Computer Simulation Conference, 2016

Enabling Debug in IoT Wireless Development and Deployment with Security Considerations.
Proceedings of the 25th IEEE North Atlantic Test Workshop, 2016

Accelerating assertion assessment using GPUs.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2016

Capturing True Workload Dependency of BTI-induced Degradation in CPU Components.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

Mobility and Direction Aware Ad-hoc on Demand Distance Vector Routing Protocol.
Proceedings of the 11th International Conference on Future Networks and Communications (FNC 2016) / The 13th International Conference on Mobile Systems and Pervasive Computing (MobiSPC 2016) / Affiliated Workshops, 2016

ECG compression for mobile sensor platforms.
Proceedings of the 13th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2016

Haptic feedback and human performance in a wearable sensor system.
Proceedings of the 2016 IEEE-EMBS International Conference on Biomedical and Health Informatics, 2016

2015
Design and Evaluation of an Intelligent Remote Tidal Volume Variability Monitoring System in E-Health Applications.
IEEE J. Biomed. Health Informatics, 2015

Architecture-Aware Real-Time Compression of Execution Traces.
ACM Trans. Embed. Comput. Syst., 2015

Movement analysis of the chest compartments and a real-time quality feedback during breathing therapy.
Netw. Model. Anal. Health Informatics Bioinform., 2015

System on chip failure rate assessment using the executable model of a system.
Computing, 2015

Efficient Reliability Analysis of Processor Datapath using Atomistic BTI Variability Models.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

FLogFS: A lightweight flash log file system.
Proceedings of the 12th IEEE International Conference on Wearable and Implantable Body Sensor Networks, 2015

2014
Dynamically Instrumenting the QEMU Emulator for Linux Process Trace Generation with the GDB Debugger.
ACM Trans. Embed. Comput. Syst., 2014

On a New Mechanism of Trigger Generation for Post-Silicon Debugging.
IEEE Trans. Computers, 2014

A Medical Cloud-Based Platform for Respiration Rate Measurement and Hierarchical Classification of Breath Disorders.
Sensors, 2014

A hybrid arithmetic transform for precision analysis of floating-point polynomial specifications.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Automated diagnosis of knee pathology using sensory data.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

Tidal volume variability and respiration rate estimation using a wearable accelerometer sensor.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014

Development of a Remote Monitoring System for Respiratory Analysis.
Proceedings of the Internet of Things. User-Centric IoT, 2014

Affordable erehabilitation monitoring platform.
Proceedings of the 2014 IEEE Canada International Humanitarian Technology Conference, 2014

Multi-sensor blind recalibration in mHealth applications.
Proceedings of the 2014 IEEE Canada International Humanitarian Technology Conference, 2014

Linear regression techniques for efficient analysis of transistor variability.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Design of an e-Health Respiration and Body Posture Monitoring System and Its Application for Rib Cage and Abdomen Synchrony Analysis.
Proceedings of the 2014 IEEE International Conference on Bioinformatics and Bioengineering, 2014

2013
Test compaction techniques for assertion-based test generation.
ACM Trans. Design Autom. Electr. Syst., 2013

"Quantum Circuit Simulations" by G. F. Viamontes, I. L. Markov and J. P. Hayes.
Quantum Inf. Process., 2013

NISHA: A fault-tolerant NoC router enabling deadlock-free Interconnection of Subnets in Hierarchical Architectures.
J. Syst. Archit., 2013

A Fault Tolerant Hierarchical Network on Chip Router Architecture.
J. Electron. Test., 2013

Managing the microprocessor course scope expansion.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Efficient Data Encoding for Improving Fault Simulation Performance on GPUs.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

An FPGA implementation of wait-free data synchronization protocols.
Proceedings of 2013 IEEE 18th Conference on Emerging Technologies & Factory Automation, 2013

Tutorial: Methodologies and tools for embedded multisensory systems based on ARM cortex M processors.
Proceedings of the International Conference on Compilers, 2013

An efficient fault-tolerant sensor fusion algorithm for accelerometers.
Proceedings of the 2013 IEEE International Conference on Body Sensor Networks, 2013

SAR Computation and Channel Modeling of Body Area Network.
Proceedings of the 8th International Conference on Body Area Networks, 2013

2012
Flexible and Reconfigurable Mismatch-Tolerant Serial Clock Distribution Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An infrastructure for debug using clusters of assertion-checkers.
Microelectron. Reliab., 2012

An FPGA implementation for a high-speed optical link with a PCIe interface.
Proceedings of the IEEE 25th International SOC Conference, 2012

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Building Blocks to Use in Innovative Non-volatile FPGA Architecture Based on MTJs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Assertion clustering for compacted test sequence generation.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

An enhanced debug-aware network interface for Network-on-Chip.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Issues in Multi-valued Multi-modal Sensor Fusion.
Proceedings of the 42nd IEEE International Symposium on Multiple-Valued Logic, 2012

MSE minimization and fault-tolerant data fusion for multi-sensor systems.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

2011
Modeling and evaluation of ring-based interconnects for Network-on-Chip.
J. Syst. Archit., 2011

Challenges of Rapidly Emerging Consumer Space Multiprocessors.
IEEE Des. Test Comput., 2011

A Brief History of Multiprocessors and EDA.
IEEE Des. Test Comput., 2011

Guest Editors' Introduction: Multicore SoC Validation with Transaction-Level Models.
IEEE Des. Test Comput., 2011

Fault tolerant glucose sensor readout and recalibration.
Proceedings of Wireless Health 2011, 2011

A distributed AXI-based platform for post-silicon validation.
Proceedings of the 29th IEEE VLSI Test Symposium, 2011

High-level design of integrated microsystems - arithmetic perspective.
Proceedings of the 2011 IEEE International Symposium on Robotic and Sensors Environments, 2011

Teaching for evolution towards embedded multi-sensor interfaces.
Proceedings of the 2011 IEEE International Conference on Microelectronic Systems Education, 2011

ERAVC: Enhanced reliability aware NoC router.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Real-time address trace compression for emulated and real system-on-chip processor core debugging.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

On Failure Rate Assessment Using an Executable Model of the System.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Debug Aware AXI-based Network Interface.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Hierarchical Embedded Logic Analyzer for Accurate Root-Cause Analysis.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

2010
Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Validating Assertion Language Rewrite Rules and Semantics With Automated Theorem Provers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Defining and Providing Coverage for Assertion-Based Dynamic Verification.
J. Electron. Test., 2010

Qualifying Serial Interface Jitter Rapidly and Cost-effectively.
J. Electron. Test., 2010

An efficient method to perform range analysis for DSP circuits.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Direct residue-to-analog conversion scheme based on Chinese Remainder Theorem.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Enabling efficient post-silicon debug by clustering of hardware-assertions.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Accelerating jitter tolerance qualification for high speed serial interfaces.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Designing and Using FPGAs beyond Classical Binary Logic: Opportunities in Nano-Scale Integration Age.
Proceedings of the ISMVL 2009, 2009

Airwolf-TG: A test generator for assertion-based dynamic verification.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2009

MYGEN: automata-based on-line test generator for assertion-based verification.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Reliability aware NoC router architecture using input channel buffer sharing.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Serial reconfigurable mismatch-tolerant clock distribution.
Proceedings of the 46th Design Automation Conference, 2009

Cache line reservation: exploring a scheme for cache-friendly object allocation.
Proceedings of the 2009 conference of the Centre for Advanced Studies on Collaborative Research, 2009

2008
Automata-based assertion-checker synthesis of PSL properties.
ACM Trans. Design Autom. Electr. Syst., 2008

BER Testing of Communication Interfaces.
IEEE Trans. Instrum. Meas., 2008

A Laboratory Setup and Teaching Methodology for Wireless and Mobile Embedded Systems.
IEEE Trans. Educ., 2008

A Quality-Driven Design Approach for NoCs.
IEEE Des. Test Comput., 2008

Proving and disproving assertion rewrite rules with automated theorem provers.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008

Built-in Clock Skew System for On-line Debug and Repair.
Proceedings of the Design, Automation and Test in Europe, 2008

2007
Scaling and Better Approximating Quantum Fourier Transform by Higher Radices.
IEEE Trans. Computers, 2007

Debug enhancements in assertion-checker generation.
IET Comput. Digit. Tech., 2007

A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Laboratory for Wireless and Mobile Embedded Systems.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

A high accuracy high throughput jitter test solution on ATE for 3GBPS and 6gbps serial-ata.
Proceedings of the 2007 IEEE International Test Conference, 2007

Assertion Checkers in Verification, Silicon Debug and In-Field Diagnosis.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Reconfigurable Clock Distribution Circuitry.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Performance Driven Layout Compaction Optimization Algorithm for Analog Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Reversible circuit technology mapping from non-reversible specifications.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Modeling Simultaneous Switching Noise-Induced Jitter for System-on-Chip Phase-Locked Loops.
Proceedings of the 44th Design Automation Conference, 2007

Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Latency Reduction of Global Traffic in Wormhole-Routed Meshes Using Hierarchical Rings for Global Routing.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Arithmetic transforms for compositions of sequential and imprecise datapaths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

An Accelerated Jitter Tolerance Test Technique on Ate for 1.5GB/S and 3GB/S Serial-ATA.
Proceedings of the 2006 IEEE International Test Conference, 2006

Arithmetic Transforms of Imprecise Datapaths by Taylor Series Conversion.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Algorithms for Compositions of Arithmetic Transforms and Their Extensions.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug.
Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
GALDS: a complete framework for designing multiclock ASICs and SoCs.
IEEE Trans. Very Large Scale Integr. Syst., 2005

Expandable and Robust Laboratory for Microprocessor Systems.
Proceedings of the 2005 International Conference on Microelectronics Systems Education, 2005

Modeling Layout Effects for Sensitivity-Based Analog Circuit Optimization.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Incorporating Ef.cient Assertion Checkers into Hardware Emulation.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Design methodology for wireless nodes with printed antennas.
Proceedings of the 42nd Design Automation Conference, 2005

2004
Design Verification by Test Vectors and Arithmetic Transform Universal Test Set.
IEEE Trans. Computers, 2004

A novel phase detector for PAM-4 clock recovery in high speed serial links.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Architectures of Increased Availability Wireless Sensor Network Nodes.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Design for Testability of FPGA Blocks.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A Versatile High Speed Bit Error Rate Testing Scheme.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Estimating Phase-Locked Loop Jitter due to Substrate Coupling: A Cyclostationary Approach.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

A novel scheme of implementing high speed AWGN communication channel emulators in FPGAs.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

FPGA Emulation of Quantum Circuits.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Layered Approach to Designing System Test Interfaces.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A globally asynchronous locally dynamic system for ASICs and SoCs.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

Testing for bit error rate in FPGA communication interfaces.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002
A Deterministic Multivariate Interpolation Algorithm for Small Finite Fields.
IEEE Trans. Computers, 2002

An FPGA Move Generator for the Game of Chess.
J. Int. Comput. Games Assoc., 2002

Identifying Redundant Wire Replacements for Synthesis and Verification.
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

The Role of Super-Fast Transforms in Speeding Up Quantum Computations.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

Design and Implementation of Error Detection and Correction Circuitry for Multilevel Memory Protection.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

A single-rail handshake CDMA correlator.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Automated SystemC to VHDL translation in hardware/software codesign.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

High speed asynchronous structures for inter-clock domain communication.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

FPGA test time reduction through a novel interconnect testing scheme.
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

An FPGA based move generator for the game of chess.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
: Identifying redundant gate replacements in verification by error modeling.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

A new PLL design for clock management applications.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Combinational verification by simulations, SAT and BDDs.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

New embedded memory architecture for enhanced yield, performance and power consumption.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A practical substrate modeling algorithm with active guardband macromodel for mixed-signal substrate coupling verification.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Arithmetic Transforms for Verifying Compositions of Sequential Datapaths.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000
Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling.
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000


FPGA clock management for low power applications (poster abstract).
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2000

Dynamic clock management for low power applications in FPGAs.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000

1999
Alternatives in Teaching System-Building Skills.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999

On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields.
Proceedings of the 1999 International Symposium on Symbolic and Algebraic Computation, 1999

1998
Using Decision Diagrams to Design ULMs for FPGAs.
IEEE Trans. Computers, 1998

Design and Implementation of the NUMAchine Multiprocessor.
Proceedings of the 35th Conference on Design Automation, 1998

1996
New Interpolation Algorithms for Multiple-Valued Reed-Muller Forms.
Proceedings of the 26th IEEE International Symposium on Multiple-Valued Logic, 1996

Using BDDs to Design ULMs for FPGAs.
Proceedings of the 1996 Fourth International Symposium on Field Programmable Gate Arrays, 1996

Experience in Designing a Large-scale Multiprocessor using Field-Programmable Devices and Advanced CAD Tools.
Proceedings of the 33st Conference on Design Automation, 1996

1995
A Multiple-Valued Reed-Muller Transform for Incompletely Specified Functions.
IEEE Trans. Computers, 1995

Reed-Muller Forms for Incompletely Specified Functions via Sparse Polynomial Interpolation.
Proceedings of the 25th IEEE International Symposium on Multiple-Valued Logic, 1995

1993
Current-Mode CMOS Galois Field Circuits.
Proceedings of the 23rd IEEE International Symposium on Multiple-Valued Logic, 1993


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