Zeeshan Sarwer

Orcid: 0000-0001-8606-3798

According to our database1, Zeeshan Sarwer authored at least 8 papers between 2021 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A single-source nine-level solar-PV inverter with quadruple voltage boosting and high reliability.
Int. J. Circuit Theory Appl., August, 2024

2023
A nine-level common ground multilevel inverter (9L-CGMLI) with reduced components and boosting ability.
Int. J. Circuit Theory Appl., August, 2023

2022
Operation, analysis, and implementation of a reduced device count asymmetrical multilevel inverter.
Int. J. Circuit Theory Appl., 2022

Design and investigation of a triple boost multilevel inverter with self-balanced switched capacitors and reduced voltage stress.
Int. J. Circuit Theory Appl., 2022

A non-isolated quasi-Z-source-based high-gain DC-DC converter.
Int. J. Circuit Theory Appl., 2022

2021
Asymmetrical multilevel inverter topology with low total standing voltage and reduced switches count.
Int. J. Circuit Theory Appl., 2021

Implementation of a Novel Variable Structure Nearest Level Modulation on Cascaded H-Bridge Multilevel Inverter.
IEEE Access, 2021

A Single Input Dual Output High Gain DC-DC Converter With Reduced Voltage Stress.
Proceedings of the IECON 2021, 2021


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