Zebo Peng

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Optimization of Assertion Placement in Time-Constrained Embedded Systems.

[BibT_eX]

[DOI]

Giuseppe Di Guglielmo

Masahiro Fujita

Proceedings of the 16th European Test Symposium, 2011

Reliability-aware frame packing for the static segment of flexray.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Embedded Software, 2011

Stability Conditions of On-line Resource Managers for Systems with Execution Time Variations.

[BibT_eX]

[DOI]

Sergiu Rafiliu

Proceedings of the 23rd Euromicro Conference on Real-Time Systems, 2011

Adaptive Temperature-Aware SoC Test Scheduling Considering Process Variation.

[BibT_eX]

[DOI]

Nima Aghaee

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Design Optimization and Synthesis of FlexRay Parameters for Embedded Control Applications.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Predictable Worst-Case Execution Time Analysis for Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

On-line Temperature-Aware Idle Time Distribution for Leakage Energy Optimization.

[BibT_eX]

[DOI]

Proceedings of the Sixth IEEE International Symposium on Electronic Design, 2011

Optimization of message encryption for distributed embedded systems with real-time constraints.

[BibT_eX]

[DOI]

Ke Jiang

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

On the quantification of sustainability and extensibility of FlexRay schedules.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

Performance optimization of error detection based on speculative reconfiguration.

[BibT_eX]

[DOI]

Adrian Alin Lifa

Proceedings of the 48th Design Automation Conference, 2011

2010

Scheduling for Fault-Tolerant Communication on the Static Segment of FlexRay.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010

Dynamic Scheduling and Control-Quality Optimization of Self-Triggered Control Applications.

[BibT_eX]

[DOI]

Proceedings of the 31st IEEE Real-Time Systems Symposium, 2010

Low Overhead Dynamic QoS Optimization under Variable Task Execution Times.

[BibT_eX]

[DOI]

Sergiu Rafiliu

Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

Value-based scheduling of distributed fault-tolerant real-time systems with soft and hard timing constraints.

[BibT_eX]

[DOI]

Viacheslav Izosimov

Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Multi-temperature testing for core-based system-on-chip.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Hardware/software optimization of error detection implementation for real-time embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Temperature-Aware SoC Test Scheduling Considering Inter-Chip Process Variation.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Design Optimization of Time- and Cost-Constrained Fault-Tolerant Embedded Systems With Checkpointing and Replication.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

Immune Genetic Algorithms for Optimization of Task Priorities and FlexRay Frame Identifiers.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Integrated scheduling and synthesis of control applications on distributed embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Analysis and optimization of fault-tolerant embedded systems with hardened processors.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Quality-driven synthesis of embedded multi-mode control systems.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Task mapping and priority assignment for soft real-time applications under deadline miss ratio constraints.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2008

Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.

[BibT_eX]

[DOI]

Soheil Samii

Mikko Selkälä

Krishnendu Chakrabarty

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Timing analysis of the FlexRay communication protocol.

[BibT_eX]

[DOI]

Real Time Syst., 2008

Analysis and Optimisation of Hierarchically Scheduled Multiprocessor Embedded Systems.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2008

Model validation for embedded systems using formal method-aided simulation.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

Test methods for crosstalk-induced delay and glitch faults in network-on-chip interconnects implementing asynchronous communication protocols.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2008

A Reconfigurable Power Conscious Core Wrapper and its Application to System-on-Chip Test Scheduling.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.

[BibT_eX]

[DOI]

J. Electron. Test., 2008

Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Temperature-Aware Task Mapping for Energy Optimization with Dynamic Voltage Scaling.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

A Simulation Methodology for Worst-Case Response Time Estimation of Distributed Real-Time Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns.

[BibT_eX]

[DOI]

Anders Larsson

Krishnendu Chakrabarty

Proceedings of the Design, Automation and Test in Europe, 2008

Scheduling of Fault-Tolerant Embedded Systems with Soft and Hard Timing Constraints.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Synthesis of Fault-Tolerant Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Temperature-Aware Voltage Selection for Energy Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Simulation-Driven Thermal-Safe Test Time Minimization for System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Energy Optimization of Multiprocessor Systems on Chip by Voltage Selection.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Fault-aware Communication Mapping for NoCs with Guaranteed Latency.

[BibT_eX]

[DOI]

Int. J. Parallel Program., 2007

Formal verification of component-based designs.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2007

Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

A heuristic for thermal-safe SoC test scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2007 IEEE International Test Conference, 2007

Transactor-based Formal Verification of Real-time Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2007

A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

Bus access optimisation for FlexRay-based distributed embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Optimized integration of test compression and sharing for SOC testing.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Real-time applications with stochastic task execution times - analysis and optimisation.

[BibT_eX]

Springer, ISBN: 978-1-4020-5505-8, 2007

2006

Quasi-Static Assignment of Voltages and Optional Cycles in Imprecise-Computation Systems With Energy Considerations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2006

Analysis and optimization of distributed real-time embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Dual Flow Nets: Modeling the control/data-flow relation in embedded systems.

[BibT_eX]

[DOI]

Mauricio Varea

Bashir M. Al-Hashimi

ACM Trans. Embed. Comput. Syst., 2006

Power-Aware Test Planning in the Early System-on-Chip Design Exploration Process.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Test Time Minimization for Hybrid BIST of Core-Based Systems.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2006

A Quasi-Static Approach to Minimizing Energy Consumption in Real-Time Systems under Reward Constraints.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2006), 2006

Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling.

[BibT_eX]

[DOI]

Soheil Samii

Krishnendu Chakrabarty

Proceedings of the 2006 IEEE International Test Conference, 2006

Mapping of Fault-Tolerant Applications with Transparency on Distributed Embedded Systems*.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Off-Line Testing of Delay Faults in NoC Interconnects.

[BibT_eX]

[DOI]

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Synthesis of Fault-Tolerant Embedded Systems with Checkpointing and Replication.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Buffer space optimisation with communication synthesis and traffic shaping for NoCs.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Formal verification of systemc designs using a petri-net based representation.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Synthesis of fault-tolerant schedules with transparency/performance trade-offs for distributed embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Power constrained and defect-probability driven SoC test scheduling with test set partitioning.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

Schedulability-driven frame packing for multicluster distributed embedded systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2005

A Wiring-Aware Approach to Minimizing Built-In Self-Test Overhead.

[BibT_eX]

[DOI]

Abdil Rashid Mohamed

J. Comput. Sci. Technol., 2005

Multiple-Constraint Driven System-on-Chip Test Time Optimization.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Abort-on-Fail Based Test Scheduling.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Optimization of Hierarchically Scheduled Heterogeneous Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Quasi-Static Scheduling for Multiprocessor Real-Time Systems with Hard and Soft Tasks.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2005), 2005

Energy minimization for hybrid BIST in a system-on-chip test environment.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Validation of Embedded Systems Using Formal Method Aided Simulation.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Power-Constrained Hybrid BIST Test Scheduling in an Abort-on-First-Fail Test Environment.

[BibT_eX]

[DOI]

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

Design Optimization of Time-and Cost-Constrained Fault-Tolerant Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

SOC Test Scheduling with Test Set Sharing and Broadcasting.

[BibT_eX]

[DOI]

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2004

Schedulability analysis of applications with stochastic task execution times.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2004

Efficient test solutions for core-based designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems.

[BibT_eX]

[DOI]

Real Time Syst., 2004

Defect-Aware SOC Test Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Optimization of Soft Real-Time Systems with Deadline Miss Ratio Constraints.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2004), 2004

Simultaneous communication and processor voltage scaling for dynamic and leakage energy reduction in time-constrained systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A Formal Verification Approach for IP-based Designs.

[BibT_eX]

[DOI]

Proceedings of the Forum on specification and Design Languages, 2004

Schedulability-Driven Partitioning and Mapping for Multi-Cluster Real-Time Systems.

[BibT_eX]

[DOI]

Proceedings of the 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June, 2004

A Heuristic for Wiring-Aware Built-In Self-Test Synthesis.

[BibT_eX]

[DOI]

Abdil Rashid Mohamed

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

A Formal Verification Methodology for IP-based Designs.

[BibT_eX]

[DOI]

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Static Scheduling of Monoprocessor Real-Time Systems composed of Hard and Soft Tasks.

[BibT_eX]

[DOI]

Proceedings of the 2nd IEEE International Workshop on Electronic Design, 2004

Design Optimization of Multi-Cluster Embedded Systems for Real-Time Application.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Quasi-Static Scheduling for Real-Time Systems with Hard and Soft Tasks.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

Hybrid BIST Test Scheduling Based on Defect Probabilities.

[BibT_eX]

[DOI]

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

Analysis and synthesis of distributed real-time embedded systems.

[BibT_eX]

[DOI]

Springer, ISBN: 978-1-4020-2872-4, 2004

2003

Modeling and formal verification of embedded systems based on a Petri net representation.

[BibT_eX]

[DOI]

J. Syst. Archit., 2003

Schedulability-driven frame packing for multi-cluster distributed embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 Conference on Languages, 2003

A Reconfigurable Power-Conscious Core Wrapper and its Application to SOC Test Scheduling.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

An efficient approach to SoC wrapper design, TAM configuration and test scheduling.

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

Schedulability Analysis for Distributed Heterogeneous Time/Event Triggered Real-Time Systems.

[BibT_eX]

[DOI]

Traian Pop

Proceedings of the 15th Euromicro Conference on Real-Time Systems (ECRTS 2003), 2003

Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Hybrid BIST Time Minimization for Core-Based Systems with STUMPS Architecture.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Schedulability Analysis and Optimization for the Synthesis of Multi-Cluster Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Design optimization of mixed time/event-triggered distributed embedded systems.

[BibT_eX]

[DOI]

Traian Pop

Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

SOC Test Time Minimization Under Multiple Constraints.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

An Integrated Framework for the Design and Optimization of SOC Test Solutions.

[BibT_eX]

[DOI]

J. Electron. Test., 2002

Editorial.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2002

Formal Verification in a Component-Based Reuse Methodology.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A Hybrid BIST Architecture and Its Optimization for SoC Testing.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Schedulability analysis of multiprocessor real-time applications with stochastic task execution times.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

High-level and hierarchical test sequence generation.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

Integrated Design and Test Generation Under Internet Based Environment MOSCITO.

[BibT_eX]

[DOI]

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Symbolic model checking of Dual Transition Petri Nets.

[BibT_eX]

[DOI]

Mauricio Varea

Bashir M. Al-Hashimi

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Holistic scheduling and analysis of mixed time/event-triggered distributed embedded systems.

[BibT_eX]

[DOI]

Traian Pop

Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Integrated Test Scheduling, Test Parallelization and TAMDesign.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

The Design and Optimization of SOC Test Solutions.

[BibT_eX]

[DOI]

Gunnar Carlsson

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Memory and Time-Efficient Schedulability Analysis of Task Sets with Stochastic Execution Time.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Real-Time Systems (ECRTS 2001), 2001

Fast Test Cost Calculation for Hybrid BIST in Digital Systems.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Hierarchical Modeling and Verification of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001

Timing simulation of digital circuits with binary decision diagrams.

[BibT_eX]

[DOI]

Raimund Ubar

Artur Jutman

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

An integrated system-on-chip test framework.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

An Approach to Incremental Design of Distributed Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Minimizing system modification in an incremental design approach.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001

Test Scheduling and Scan-Chain Division under Power Constraint.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Scheduling with bus access optimization for distributed embedded systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

An improved register-transfer level functional partitioning approach for testability.

[BibT_eX]

[DOI]

Laurence Tianruo Yang

J. Syst. Archit., 2000

Verification of Embedded Systems using a Petri Net based Representation.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

Modeling of Real-Time Embedded Systems in an Object-Oriented Design Environment with UML.

[BibT_eX]

[DOI]

Proceedings of the 3rd International Symposium on Object-Oriented Real-Time Distributed Computing (ISORC 2000), 2000

Definitions of Equivalence for Transformational Synthesis of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 6th International Conference on Engineering of Complex Computer Systems (ICECCS 2000), 2000

Formal Coverification of Embedded Systems Using Model Checking.

[BibT_eX]

[DOI]

Proceedings of the 26th EUROMICRO 2000 Conference, 2000

Schedulability analysis for systems with data and control dependencies.

[BibT_eX]

[DOI]

Proceedings of the 12th Euromicro Conference on Real-Time Systems (ECRTS 2000), 2000

Test Cost Minimization for Hybrid Bist.

[BibT_eX]

[DOI]

Gert Jervan

Raimund Ubar

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Performance estimation for embedded systems with data and control dependencies.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Incremental Testability Analysis for Partial Scan Selection and Design Transformations.

[BibT_eX]

[DOI]

Laurence Tianruo Yang

J. Electron. Test., 1999

An Improved Scheduling Technique for Time-Triggered Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th EUROMICRO '99 Conference, 1999

Scheduling with optimized communication for time-triggered embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

Estimation and Consideration of Interconnection Delays during High-Level Synthesis.

[BibT_eX]

[DOI]

Jonas Hallberg

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th EUROMICRO '98 Conference, 1998

An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis.

[BibT_eX]

[DOI]

Laurence Tianruo Yang

Proceedings of the 1998 Design, 1998

Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

1997

Inter-domain movement of functionality as a repartitioning strategy for hardware/software co-design.

[BibT_eX]

Erik Stoy

J. Syst. Archit., 1997

Post-synthesis back-annotation of timing information in behavioral VHDL.

[BibT_eX]

[DOI]

J. Syst. Archit., 1997

System Level Hardware/Software Partitioning Based on Simulated Annealing and Tabu Search.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1997

A controller testability analysis and enhancement technique.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Synthesis of systems specified as interacting VHDL processes.

[BibT_eX]

[DOI]

Integr., 1996

Hardware/Software Partitioning with Iterative Improvement Heuristics.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on System Synthesis, 1996

Automatic Parallelization of a Petri Net-Based Design Representation for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 22rd EUROMICRO Conference '96, 1996

Hardware/software partitioning of VHDL system specifications.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1996

1995

An Efficient and Economic Partitioning Approach for Testability.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1995, 1995

Timing constraint specification and synthesis in behavioral VHDL.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'95, 1995

1994

Automated transformation of algorithms into register-transfer level implementations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An Integrated Modelling Technique for Hardware/Software Systems.

[BibT_eX]

[DOI]

Erik Stoy

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Testability analysis and improvement from VHDL behavioral specifications.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Synthesis of VHDL concurrent processes.

[BibT_eX]

[DOI]

Proceedings of the Proceedings EURO-DAC'94, 1994

Timing analysis and conditional scheduling in a real-time system design environment.

[BibT_eX]

[DOI]

Anders Törne

Proceedings of the Sixth Euromicro Workshop on Real-Time Systems, 1994

VHDL system-level specification and partitioning in a hardware/software co-synthesis environment.

[BibT_eX]

[DOI]

Alexa Doboli

Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993

A Petri Net Based Modelling and Synthesis Technique for Real-Time Systems.

[BibT_eX]

[DOI]

Anders Törne

Proceedings of the Fifth Euromicro Workshop on Real-Time Systems, 1993

1992

Digital system simulation with VHDL in a high-level synthesis system.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1992

An approach to testability analysis and improvement for VLSI systems.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1992

Compiling VHDL into a high-level synthesis design representation.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1992

1991

Design of clocking schemes in high-level synthesis.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1991

Testability measure with reconvergent fanout analysis and its applications.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1991

1990

Testability analysis in a VLSI high-level synthesis system.

[BibT_eX]

[DOI]

Microprocessing and Microprogramming, 1990

1988

Let's design asynchronous VLSI systems.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1988

Parallelism extraction from sequential programs for VLSI applications.

[BibT_eX]

[DOI]

Microprocess. Microprogramming, 1988

Semantics of a Parallel Computation Model and its Applications in Digital Hardware Design.

[BibT_eX]

Proceedings of the International Conference on Parallel Processing, 1988

1987

Microprogramming implementation of timed Petri nets.

[BibT_eX]

[DOI]

Integr., 1987

1986

Construction of Asynchronous Concurrent Systems from their Behavioral Specifications.

[BibT_eX]

Proceedings of the Information Processing 86, 1986

Synthesis of VLSI systems with the CAMAD design aid.

[BibT_eX]

[DOI]