Zdenek Kotásek

According to our database, Zdenek Kotásek authored at least 89 papers between 1995 and 2021.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2021

Testing Embedded Software Through Fault Injection: Case Study on Smart Lock.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Automatically-Designed Fault-Tolerant Systems: Failed Partitions Recovery.

Jakub Lojda, Richard Panek, Zdenek Kotásek

Proceedings of the IEEE East-West Design & Test Symposium, 2021

Reliability Analysis of the FPGA Control System with Reconfiguration Hardening.

Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Automatic Design of Fault-Tolerant Systems for VHDL and SRAM-based FPGAs.

Jakub Lojda, Richard Panek, Zdenek Kotásek

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

2020

Reliability Analysis of Reconfiguration Controller for FPGA-Based Fault Tolerant Systems: Case Study.

Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

Evaluation Platform For Testing Fault Tolerance: Testing Reliability of Smart Electronic Locks.

Jakub Podivinsky, Jakub Lojda, Richard Panek, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Iterative Algorithm for Multidimensional Pareto Frontiers Intersection Determination.

Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

Analysis of Software-Implemented Fault Tolerance: Case Study on Smart Lock.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the IEEE East-West Design & Test Symposium, 2020

Hardening of Smart Electronic Lock Software against Random and Deliberate Faults.

Jakub Lojda, Richard Panek, Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Zdenek Kotásek

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Automatic Design of Reliable Systems Based on the Multiple-choice Knapsack Problem.

Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Martin Krcma, Zdenek Kotásek

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

2019

Coarse-Grained TMR Soft-Core Processor Fault Tolerance Methods and State Synchronization for Run-Time Fault Recovery.

Karel Szurman, Zdenek Kotásek

Proceedings of the IEEE Latin American Test Symposium, 2019

Extended Reliability Analysis of Fault-Tolerant FPGA-based Robot Controller.

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek

Proceedings of the IEEE Latin American Test Symposium, 2019

Reliability Indicators for Automatic Design and Analysis of Fault-Tolerant FPGA Systems.

Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the IEEE Latin American Test Symposium, 2019

Detecting hard synapses faults in artificial neural networks.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the IEEE Latin American Test Symposium, 2019

Multidimensional Pareto Frontiers Intersection Determination and Processor Optimization Case Study.

Jakub Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Testing Reliability of Smart Electronic Locks: Analysis and the First Steps Towards.

Ondrej Cekan, Jakub Podivinsky, Jakub Lojda, Richard Panek, Martin Krcma, Zdenek Kotásek

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Run-Time Reconfigurable Fault Tolerant Architecture for Soft-Core Processor NEO430.

Karel Szurman, Zdenek Kotásek

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

2018

An Experimental Evaluation of Fault-Tolerant FPGA-Based Robot Controller.

Jakub Podivinsky, Jakub Lojda, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

A Processor Optimization Framework for a Selected Application.

Jalab Podivinsky, Ondrej Cekan, Martin Krcma, Radek Burget, Tomas Hruska, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Partial Dynamic Reconfiguration in an FPGA-based Fault-Tolerant System: Simulation-based Evaluation.

Richard Panek, Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis.

Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Input and Output Generation for the Verification of ALU: A Use Case.

Ondrej Cekan, Richard Panek, Zdenek Kotásek

Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018

Evaluation Platform for Testing Fault Tolerance Properties: Soft-core Processor-Based Experimental Robot Controller.

Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Zdenek Kotásek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

FT-EST Framework: Reliability Estimation for the Purposes of Fault-Tolerant System Design Automation.

Jakub Lojda, Jakub Podivinsky, Ondrej Cekan, Richard Panek, Zdenek Kotásek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Program Generation Through a Probabilistic Constrained Grammar.

Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017

Functional verification based platform for evaluating fault tolerance properties.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Marcela Zachariásová, Martin Krcma, Zdenek Kotásek

Microprocess. Microsystems, 2017

Comparison of FPNNs models approximation capabilities and FPGA resources utilization.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the 13th IEEE International Conference on Intelligent Computer Communication and Processing, 2017

Data types and operations modifications: A practical approach to fault tolerance in HLS.

Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek, Martin Krcma

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Redundant data types and operations in HLS and their use for a robot controller unit fault tolerance evaluation.

Jakub Lojda, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Triple modular redundancy used in field programmable neural networks.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the 2017 IEEE East-West Design & Test Symposium, 2017

Reliability Analysis and Improvement of FPGA-Based Robot Controller.

Jakub Podivinsky, Jakub Lojda, Ondrej Cekan, Richard Panek, Zdenek Kotásek

Proceedings of the Euromicro Conference on Digital System Design, 2017

A Probabilistic Context-Free Grammar Based Random Test Program Generation.

Ondrej Cekan, Zdenek Kotásek

Proceedings of the Euromicro Conference on Digital System Design, 2017

2016

Functional verification as a tool for monitoring impact of faults in SRAM-based FPGAs.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

HLS-based fault tolerance approach for SRAM-based FPGAs.

Jakub Lojda, Jakub Podivinsky, Martin Krcma, Zdenek Kotásek

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Implementation of fault tolerant techniques into FPNNs.

Martin Krcma, Zdenek Kotásek, Jakub Lojda

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Random stimuli generation based on a stochastic context-free grammar.

Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Regression Test Suites Optimization for Application-specific Instruction-Set Processors and Their Use for Dependability Analysis.

Marcela Zachariásová, Michaela Kekelyova-Beleova, Zdenek Kotásek

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Verification of Robot Controller for Evaluating Impacts of Faults in Electro-Mechanical Systems.

Jakub Podivinsky, Ondrej Cekan, Jakub Lojda, Zdenek Kotásek

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

2015

The evaluation platform for testing fault-tolerance methodologies in electro-mechanical applications.

Jakub Podivinsky, Ondrej Cekan, Marcela Simková, Zdenek Kotásek

Microprocess. Microsystems, 2015

Fault tolerant Field Programmable Neural Networks.

Martin Krcma, Zdenek Kotásek, Jan Kastil

Proceedings of the Nordic Circuits and Systems Conference, 2015

Automation and Optimization of Coverage-driven Verification.

Marcela Simková, Zdenek Kotásek

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Software Fault Tolerance: The Evaluation by Functional Verification.

Ondrej Cekan, Jakub Podivinsky, Zdenek Kotásek

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

FPGA Prototyping and Accelerated Verification of ASIPs.

Jakub Podivinsky, Marcela Simková, Ondrej Cekan, Zdenek Kotásek

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Mapping Trained Neural Networks to FPNNs.

Martin Krcma, Jan Kastil, Zdenek Kotásek

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

Application of Evolutionary Algorithms for Regression Suites Optimization.

Michaela Beleova, Zdenek Kotásek, Marcela Simková, Toma Hruka

Proceedings of the 18th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2015

2014

State Synchronization after Partial Reconfiguration of Fault Tolerant CAN Bus Control System.

Karel Szurman, Lukas Miculka, Zdenek Kotásek

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Automatic Construction of On-line Checking Circuits Based on Finite Automata.

Lucie Matuova, Jan Kastil, Zdenek Kotásek

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Generic partial dynamic reconfiguration controller for transient and permanent fault mitigation in fault tolerant systems implemented into FPGA.

Lukas Miculka, Zdenek Kotásek

Proceedings of the 17th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2014

2013

Fault tolerant system design and SEU injection based testing.

Martin Straka, Jan Kastil, Zdenek Kotásek, Lukas Miculka

Microprocess. Microsystems, 2013

Automated Functional Verification of Application Specific Instruction-set Processors.

Marcela Simková, Zdenek Prikryl, Zdenek Kotásek, Tomas Hruska

Proceedings of the Embedded Systems: Design, Analysis and Verification, 2013

Methodology for Fault Tolerant System Design Based on FPGA into Limited Redundant Area.

Lukas Miculka, Martin Straka, Zdenek Kotásek

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Fault tolerant CAN bus control system implemented into FPGA.

Karel Szurman, Jan Kastil, Martin Straka, Zdenek Kotásek

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

Analysis and comparison of functional verification and ATPG for testing design reliability.

Marcela Simková, Zdenek Kotásek, Cristiana Bolchini

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2012

pecial CAI Section Devoted to MEMICS '11: Preface.

Zdenek Kotásek, Lukás Sekanina, Tomás Vojnar, Jan Bouda, Ivana Cerná

Comput. Informatics, 2012

Dependability Analysis of Fault Tolerant Systems Based on Partial Dynamic Reconfiguration Implemented into FPGA.

Jan Kastil, Martin Straka, Lukas Miculka, Zdenek Kotásek

Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Test platform for fault tolerant systems design properties verification.

Martin Straka, Lukas Miculka, Jan Kastil, Zdenek Kotásek

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011

SEU Simulation Framework for Xilinx FPGA: First Step towards Testing Fault Tolerant Systems.

Martin Straka, Jan Kastil, Zdenek Kotásek

Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Advanced fault tolerant bus for multicore system implemented in FPGA.

Martin Straka, Jan Kastil, Jaroslav Novotný, Zdenek Kotásek

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Decreasing test time by scan chain reorganization.

Pavel Bartos, Zdenek Kotásek, Jan Dohnal

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

The Use of Genetic Algorithm to Reduce Power Consumption during Test Application.

Jaroslav Skarvada, Zdenek Kotásek, Josef Strnadel

Proceedings of the Evolvable Systems: From Biology to Hardware, 2010

Fault Tolerant Structure for SRAM-Based FPGA via Partial Dynamic Reconfiguration.

Martin Straka, Jan Kastil, Zdenek Kotásek

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

The Use of Genetic Algorithm to Derive Correlation Between Test Vector and Scan Register Sequences and Reduce Power Consumption.

Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Modern fault tolerant architectures based on partial dynamic reconfiguration in FPGAs.

Martin Straka, Jan Kastil, Zdenek Kotásek

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Reduction of power dissipation through parallel optimization of test vector and scan register sequences.

Zdenek Kotásek, Jaroslav Skarvada, Josef Strnadel

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

High Availability Fault Tolerant Architectures Implemented into FPGAs.

Martin Straka, Zdenek Kotásek

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008

Evolution of synthetic RTL benchmark circuits with predefined testability.

Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek

ACM Trans. Design Autom. Electr. Syst., 2008

Testability analysis based on the identification of testable blocks with predefined properties.

Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman

Microprocess. Microsystems, 2008

Polymorphic Gates in Design and Test of Digital Circuits.

Lukás Sekanina, Lukás Starecek, Zdenek Kotásek, Zbysek Gajda

Int. J. Unconv. Comput., 2008

Preface.

Milan Ceska, Zdenek Kotásek, Mojmír Kretínský, Ludek Matyska, Tomás Vojnar

Proceedings of the International Doctoral Workshop on Mathematical and Engineering Methods in Computer Science, 2008

Measuring CADeT Performance by Means of FITTest_BENCH06 Benchmark Circuits.

Josef Strnadel, Tomas Pecenka, Zdenek Kotásek

Comput. Informatics, 2008

Digital Systems Architectures Based on On-line Checkers.

Martin Straka, Zdenek Kotásek, Jan Winter

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Power Conscious RTL Test Scheduling.

Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Reduction of Test Vectors Volume by Means of Gate-Level Reconfiguration.

Lukás Starecek, Lukás Sekanina, Zdenek Kotásek

Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008

2007

Online Protocol Testing for FPGA Based Fault Tolerant Systems.

Jiri Tobola, Zdenek Kotásek, Jan Korenek, Tomás Martínek, Martin Straka

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Checker Design for On-line Testing of Xilinx FPGA Communication Protocols.

Martin Straka, Jiri Tobola, Zdenek Kotásek

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

SET: Interactive Tool for Learning and Training Scan-Based DFT Principles and Their Consequences to Parameters of Embedded System.

Josef Strnadel, Zdenek Kotásek

Proceedings of the 13th Annual IEEE International Conference and Workshop on Engineering of Computer Based Systems (ECBS 2006), 2006

Testability Estimation Based on Controllability and Observability Parameters.

Tomas Pecenka, Josef Strnadel, Zdenek Kotásek, Lukás Sekanina

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Novel Logic Circuits Controlled by Vdd: Transistor-Level Simulations of Polymorphic Combinational Modules.

Lukás Sekanina, Lukás Starecek, Zdenek Kotásek

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

FITTest_BENCH06: A New Set of Benchmark Circuits Reflecting Diagnostic Properties.

Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Evolution of Multifunctional Combinational Modules Controlled by the Power Supply Voltage.

Lukás Sekanina, Lukás Starecek, Zbysek Gajda, Zdenek Kotásek

Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006

2005

Automatic Discovery of RTL Benchmark Circuits with Predefined Testability Properties.

Tomas Pecenka, Zdenek Kotásek, Lukás Sekanina, Josef Strnadel

Proceedings of the 2005 NASA / DoD Conference on Evolvable Hardware (EH 2005), 29 June, 2005

Educational Tool for the Demonstration of DfT Principles Based on Scan Methodologies.

Josef Strnadel, Zdenek Kotásek

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2004

The Identification of registers in RTL Structures for the Test Application.

Daniel Mika, Josef Strnadel, Zdenek Kotásek

Proceedings of the International Symposium on Leveraging Applications of Formal Methods, 2004

2003

Test scheduling for embedded systems.

Zdenek Kotásek, Daniel Mika, Josef Strnadel

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

Testability Improvements Based on the Combination of Analytical and Evolutionary Approaches at RT Level.

Josef Strnadel, Zdenek Kotásek

Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

2000

Formal Approach to the RTL Testability Analysis.

Zdenek Kotásek, Richard Ruzicka, Jan Hlavicka

Proceedings of the 1st Latin American Test Workshop, 2000

1997

RT Level Test Scheduling.

Jan Blatný, Zdenek Kotásek, Jan Hlavicka

Comput. Artif. Intell., 1997

RT level testability analysis to reduce test application time.

Zdenek Kotásek, F. Zboril

Proceedings of the 23rd EUROMICRO Conference '97, 1997

1995

I-Path Analysis.

Jan Blatný, Zdenek Kotásek

Comput. Artif. Intell., 1995