Zarrin Tasnim Sworna

According to our database, Zarrin Tasnim Sworna authored at least 12 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

The ethical implications of Chatbot developments for conservation expertise.

Zarrin Tasnim Sworna, Danilo Urzedo, Andrew J. Hoskins, Catherine J. Robinson

AI Ethics, November, 2024

2023

NLP methods in host-based intrusion detection systems: A systematic review and future directions.

Zarrin Tasnim Sworna, Zahra Mousavi, Muhammad Ali Babar

J. Netw. Comput. Appl., November, 2023

APIRO: A Framework for Automated Security Tools API Recommendation.

Zarrin Tasnim Sworna, Chadni Islam, Muhammad Ali Babar

ACM Trans. Softw. Eng. Methodol., January, 2023

IRP2API: Automated Mapping of Cyber Security Incident Response Plan to Security Tools' APIs.

Zarrin Tasnim Sworna, Muhammad Ali Babar, Anjitha Sreekumar

Proceedings of the IEEE International Conference on Software Analysis, 2023

Security Tools' API Recommendation Using Machine Learning.

Zarrin Tasnim Sworna, Anjitha Sreekumar, Chadni Islam, Muhammad Ali Babar

Proceedings of the 18th International Conference on Evaluation of Novel Approaches to Software Engineering, 2023

2022

"I think this is the most disruptive technology": Exploring Sentiments of ChatGPT Early Adopters using Twitter Data.

Mubin Ul Haque, Isuru Dharmadasa, Zarrin Tasnim Sworna, Roshan Namal Rajapakse, Hussain Ahmad

CoRR, 2022

A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design.

Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal

CoRR, 2022

2018

A Fast FPGA-Based BCD Adder.

Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu, Ashis Kumer Biswas

Circuits Syst. Signal Process., 2018

2017

An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem.

Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu, Lafifa Jamal, Ashis Kumer Biswas

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016

Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array.

Zarrin Tasnim Sworna, Mubin Ul Haque, Nazma Tara, Hafiz Md. Hasan Babu, Ashis Kumer Biswas

IET Circuits Devices Syst., 2016

An Improved Design of a Reversible Fault Tolerant LUT-based FPGA.

Mubin Ul Haque, Zarrin Tasnim Sworna, Hafiz Md. Hasan Babu

Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

A LUT-based matrix multiplication using neural networks.

Zarrin Tasnim Sworna, Mubin Ul Haque, Hafiz Md. Hasan Babu

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016