Zarin Tasnim Sandhie

According to our database, Zarin Tasnim Sandhie authored at least 7 papers between 2018 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

Design of novel 3T ternary DRAM with single word-line using CNTFET.

Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury

Microelectron. J., 2022

Investigation of Multiple-valued Logic Technologies for Beyond-binary Era.

Zarin Tasnim Sandhie, Jill Arvindbhai Patel, Farid Uddin Ahmed, Masud H. Chowdhury

ACM Comput. Surv., 2022

2021

A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits.

Farid Uddin Ahmed, Zarin Tasnim Sandhie, Liaquat Ali, Masud H. Chowdhury

IEEE Access, 2021

2020

Design of Ternary Master-Slave D-Flip Flop using MOS-GNRFET.

Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

GNRFET based Ternary Logic - Prospects and Potential Implementation.

Zarin Tasnim Sandhie, Farid Uddin Ahmed, Masud H. Chowdhury

Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020

An Implementation of External Capacitor-less Low-DropOut Voltage Regulator in 45nm Technology with Output Voltage Ranging from 0.4V-1.2V.

Farid Uddin Ahmed, Zarin Tasnim Sandhie, Masud H. Chowdhury

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2018

Ternary Device using Graphene Memcapacitor for Post Binary Era.

Jill Arvindbhai Patel, Zarin Tasnim Sandhie, Masud H. Chowdhury

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018