Zainab Aizaz

According to our database, Zainab Aizaz authored at least 6 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2024

Approximate Row-Merging-Based Multipliers for Neural Network Acceleration on FPGAs.

Zainab Aizaz, Kavita Khare, Aizaz Tirmizi

IEEE Embed. Syst. Lett., June, 2024

2023

ASMPEC: Approximate-Sum-Based Mapping of Partial Products With Error Correction for Softcore Multipliers on FPGAs.

Zainab Aizaz, Kavita Khare

IEEE Trans. Circuits Syst. II Express Briefs, December, 2023

FASBM: FPGA-specific Approximate Sum-based Booth multipliers for energy efficient Hardware Acceleration of Image Processing and Machine Learning Applications.

Zainab Aizaz, Kavita Khare, Aizaz Tirmizi

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

A1RL: Approximate 1-Row-LUT-Based Low-Power Signed Multipliers for DSP and Machine Learning Applications on FPGAs.

Zainab Aizaz, Kavita Khare, Mohd Anas Khan, Mahesh Kumar Singh, Vaithiyanathan Dhandapani

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

Area and Power Efficient Truncated Booth Multipliers Using Approximate Carry-Based Error Compensation.

Zainab Aizaz, Kavita Khare

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Energy efficient approximate booth multipliers using compact error compensation circuit for mitigation of truncation error.

Zainab Aizaz, Kavita Khare

Int. J. Circuit Theory Appl., 2022