Zaid Al-Ars
Orcid: 0000-0001-7670-8572
According to our database1,
Zaid Al-Ars
authored at least 184 papers
between 2000 and 2024.
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Bibliography
2024
Hardware-Accelerator Design by Composition: Dataflow Component Interfaces With Tydi-Chisel.
IEEE Trans. Very Large Scale Integr. Syst., December, 2024
Fully Pipelined FPGA Acceleration of Binary Convolutional Neural Networks with Neural Architecture Search.
J. Circuits Syst. Comput., 2024
CoRR, 2024
CoRR, 2024
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2024
Proceedings of the 2024 IEEE Nordic Circuits and Systems Conference (NorCAS), 2024
Proceedings of the 34th IEEE International Workshop on Machine Learning for Signal Processing, 2024
Proceedings of the International Joint Conference on Neural Networks, 2024
Learning Structured Sparsity for Efficient Nanopore DNA Basecalling Using Delayed Masking.
Proceedings of the 15th ACM International Conference on Bioinformatics, 2024
2023
Distributed Ledger Technol. Res. Pract., September, 2023
Proceedings of the Joint Proceedings of Workshops at the 49th International Conference on Very Large Data Bases (VLDB 2023), Vancouver, Canada, August 28, 2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
OctoRay: Framework for Scalable FPGA Cluster Acceleration of Python Big Data Applications.
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the IEEE International Conference on Quantum Computing and Engineering, 2023
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2023
Proceedings of the IEEE Intelligent Vehicles Symposium, 2023
NLICE: Synthetic Medical Record Generation for Effective Primary Healthcare Differential Diagnosis.
Proceedings of the 23rd IEEE International Conference on Bioinformatics and Bioengineering, 2023
2022
A Toolchain for Streaming Dataflow Accelerator Designs for Big Data Analytics: Defining an IR for Composable Typed Streaming Dataflow Designs.
CoRR, 2022
Tydi-lang: a language for typed streaming hardware - A manual for future Tydi-lang compiler developers.
CoRR, 2022
QPack Scores: Quantitative performance metrics for application-oriented quantum computer benchmarking.
CoRR, 2022
Benchmarking Apache Arrow Flight - A wire-speed protocol for data transfer, querying and microservices.
CoRR, 2022
Towards an Automatic Diagnosis of Peripheral and Central Palsy Using Machine Learning on Facial Features.
CoRR, 2022
Bioinform., 2022
Communication-Efficient Cluster Scalable Genomics Data Processing Using Apache Arrow Flight.
Proceedings of the 21st International Symposium on Parallel and Distributed Computing, 2022
SALoBa: Maximizing Data Locality and Workload Balance for Fast Sequence Alignment on GPUs.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022
Fidel: Reconstructing Private Training Samples from Weight Updates in Federated Learning.
Proceedings of the 9th International Conference on Internet of Things: Systems, 2022
Proceedings of the 33rd British Machine Vision Conference 2022, 2022
Proceedings of the Artificial General Intelligence - 15th International Conference, 2022
2021
Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project.
Microprocess. Microsystems, November, 2021
Generating High-Performance FPGA Accelerator Designs for Big Data Analytics with Fletcher and Apache Arrow.
J. Signal Process. Syst., 2021
QKSA: Quantum Knowledge Seeking Agent - resource-optimized reinforcement learning using quantum process tomography.
CoRR, 2021
QPack: Quantum Approximate Optimization Algorithms as universal benchmark for quantum computers.
CoRR, 2021
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2021
AutoReCon: Neural Architecture Search-based Reconstruction for Data-free Compression.
Proceedings of the Thirtieth International Joint Conference on Artificial Intelligence, 2021
Proceedings of the ICCDE 2021: 7th International Conference on Computing and Data Engineering, Phuket, Thailand, January 15, 2021
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2021, 2021
Proceedings of the International Conference on Field-Programmable Technology, 2021
2020
J. Signal Process. Syst., 2020
ACM Trans. Archit. Code Optim., 2020
IEEE Micro, 2020
Privacy-Preserving Object Detection & Localization Using Distributed Machine Learning: A Case Study of Infant Eyeblink Conditioning.
CoRR, 2020
SoFAr: Shortcut-based Fractal Architectures for Binary Convolutional Neural Networks.
CoRR, 2020
CoRR, 2020
BioDynaMo: an agent-based simulation platform for scalable computational biology research.
CoRR, 2020
CoRR, 2020
Optimizing performance of GATK workflows using Apache Arrow In-Memory data framework.
BMC Genom., 2020
BMC Bioinform., 2020
IEEE Access, 2020
REAF: Reducing Approximation of Channels by Reducing Feature Reuse Within Convolution.
IEEE Access, 2020
Proceedings of the 28th Euromicro International Conference on Parallel, 2020
Stairway to Abstraction: an Iterative Algorithm for Whisker Detection in Video Frames.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the 2020 International Joint Conference on Neural Networks, 2020
Proceedings of the International Conference on Field-Programmable Technology, 2020
Proceedings of the ICBBB 2020: 10th International Conference on Bioscience, 2020
Synthesis-Free, Flexible and Fast Hardware Library for Biophysically Plausible Neurosimulations.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020
Proceedings of the ECAI 2020 - 24th European Conference on Artificial Intelligence, 29 August-8 September 2020, Santiago de Compostela, Spain, August 29 - September 8, 2020, 2020
Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
J. Signal Process. Syst., 2019
Frame-based Programming, Stream-Based Processing for Medical Image Processing Applications.
J. Signal Process. Syst., 2019
ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications.
J. Signal Process. Syst., 2019
J. Electron. Test., 2019
BMC Genom., 2019
Correction to: GASAL2: a GPU accelerated sequence alignment library for high-throughput NGS data.
BMC Bioinform., 2019
BMC Bioinform., 2019
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019
A Fine-Grained Parallel Snappy Decompressor for FPGAs Using a Relaxed Execution Model.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems.
Proceedings of the 16th ACM International Conference on Computing Frontiers, 2019
Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019
Supporting Columnar In-memory Formats on FPGA: The Hardware Design of Fletcher for Apache Arrow.
Proceedings of the Applied Reconfigurable Computing - 15th International Symposium, 2019
2018
Comput. Biol. Chem., 2018
Proceedings of the High Performance Computing, 2018
GPU-based stochastic-gradient optimization for non-rigid medical image registration in time-critical applications.
Proceedings of the Medical Imaging 2018: Image Processing, 2018
Proceedings of the 2018 IEEE East-West Design & Test Symposium, 2018
An industrial case study of low cost adaptive voltage scaling using delay test patterns.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Industrial evaluation of transition fault testing for cost effective offline adaptive voltage scaling.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2018
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018
Comparative Analysis of System-Level Acceleration Techniques in Bioinformatics: A Case Study of Accelerating the Smith-Waterman Algorithm for BWA-MEM.
Proceedings of the 18th IEEE International Conference on Bioinformatics and Bioengineering, 2018
Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018
2017
Proceedings of the High Performance Computing, 2017
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Using transition fault test patterns for cost effective offline performance estimation.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017
Proceedings of the 2017 IEEE International Conference on Bioinformatics and Biomedicine, 2017
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017
High Performance Streaming Smith-Waterman Implementation with Implicit Synchronization on Intel FPGA using OpenCL.
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017
Proceedings of the 17th IEEE International Conference on Bioinformatics and Bioengineering, 2017
SparkGA: A Spark Framework for Cost Effective, Fast and Accurate DNA Analysis at Scale.
Proceedings of the 8th ACM International Conference on Bioinformatics, 2017
VLIW-Based FPGA Computation Fabric with Streaming Memory Hierarchy for Medical Imaging Applications.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017
2016
An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping with BWAMEM.
SIGARCH Comput. Archit. News, 2016
CoRR, 2016
Power-efficiency analysis of accelerated BWA-MEM implementations on heterogeneous computing platforms.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2016
Proceedings of the 11th International Design & Test Symposium, 2016
Power-Efficient Accelerated Genomic Short Read Mapping on Heterogeneous Computing Platforms.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016
Challenges of using on-chip performance monitors for process and environmental variation compensation.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016
Proceedings of the IEEE International Conference on Bioinformatics and Biomedicine, 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
Proceedings of the 2nd Annual International Symposium on Information Management and Big Data, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Calculation of worst-case execution time for multicore processors using deterministic execution.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 IEEE International Conference on Bioinformatics and Biomedicine, 2015
Proceedings of the 2015 IEEE International Conference on Bioinformatics and Biomedicine, 2015
Heterogeneous Hardware Accelerators with Hybrid Interconnect: An Automated Design Approach.
Proceedings of the 2015 International Conference on Advanced Computing and Applications, 2015
2014
Automated Hybrid Interconnect Design for FPGA Accelerators Using Data Communication Profiling.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the 3rd International Conference on Context-Aware Systems and Applications, 2014
2013
Proceedings of the 8th International Design and Test Symposium, 2013
Accurate and efficient identification of worst-case execution time for multicore processors: A survey.
Proceedings of the 8th International Design and Test Symposium, 2013
Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms.
Proceedings of the 8th International Design and Test Symposium, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
2012
DetLock: Portable and Efficient Deterministic Execution for Shared Memory Multicore Systems.
Proceedings of the 2012 SC Companion: High Performance Computing, 2012
A heuristic-based communication-aware hardware optimization approach in heterogeneous multicore systems.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Rule-based data communication optimization using quantitative communication profiling.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Survey of fault tolerance techniques for shared memory multicore/multiprocessor systems.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 6th IEEE International Design and Test Workshop, 2011
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
Proceedings of the 20th IEEE Asian Test Symposium, 2011
2010
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 5th International Design and Test Workshop, 2010
Proceedings of the 5th International Design and Test Workshop, 2010
2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
Proceedings of the Eighteentgh Asian Test Symposium, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the 2008 IEEE International Test Conference, 2008
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
2007
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007
Proceedings of the 12th European Test Symposium, 2007
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007
2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Proceedings of the 2006 IEEE International Test Conference, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005
Proceedings of the 2005 Design, 2005
Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005
2004
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004
Proceedings of the 9th European Test Symposium, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004
2003
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
IEEE Trans. Computers, 2003
J. Electron. Test., 2003
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003
Proceedings of the 2003 Design, 2003
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
Analyzing the Impact of Process Variations on DRAM Testing Using Border Resistance Traces.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003
2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Proceedings of the 2002 Design, 2002
Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002
2001
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001
Simulation based analysis of temperature effect on the faulty behavior of embedded DRAMs.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000