Zahra Azad

Orcid: 0000-0001-6701-1052

According to our database1, Zahra Azad authored at least 8 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

2022
RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

2021
AI Tax in Mobile SoCs: End-to-end Performance Analysis of Machine Learning in Smartphones.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

Hardware Acceleration for DBMS Machine Learning Scoring: Is It Worth the Overheads?
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2021

2020
BlackParrot: An Agile Open-Source RISC-V Multicore for Accelerator SoCs.
IEEE Micro, 2020

2019
AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches.
IEEE Trans. Emerg. Top. Comput., 2019

2018
ORIENT: Organized interleaved ECCs for new STT-MRAM caches.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors.
IEEE Trans. Parallel Distributed Syst., 2017


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