Zaher S. Andraus

According to our database, Zaher S. Andraus authored at least 7 papers between 2004 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Automatic Formal Verification of Control Logic in Hardware Designs.

Zaher S. Andraus

PhD thesis, 2009

A branch and bound algorithm for extracting smallest minimal unsatisfiable subformulas.

Mark H. Liffiton, Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah

Constraints An Int. J., 2009

2008

Reveal: A Formal Verification Tool for Verilog Designs.

Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah

Proceedings of the Logic for Programming, 2008

2006

Refinement strategies for verification methods based on datapath abstraction.

Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005

A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas.

Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva, Karem A. Sakallah

Proceedings of the Theory and Applications of Satisfiability Testing, 2005

2004

AMUSE: a minimally-unsatisfiable subformula extractor.

Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov

Proceedings of the 41th Design Automation Conference, 2004

Automatic abstraction and verification of verilog models.

Zaher S. Andraus, Karem A. Sakallah

Proceedings of the 41th Design Automation Conference, 2004