Yvon Savaria

Jean-Pierre David

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Prediction Model for Implementing DVS in Single-Rail Bundled-Data Handshake-Free Asynchronous Circuits.

[BibT_eX]

[DOI]

Maryem Benyoussef

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Toward In-System Monitoring of OpenCL-Based Designs on FPGA.

[BibT_eX]

[DOI]

Hachem Bensalem

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Versatile SoC/SiP Sensor Interface for Industrial Applications: Design Considerations.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Microelectronics, 2019

AnARM: A 28nm Energy Efficient ARM Processor Based on Octasic Asynchronous Technology.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019

Memristor Emulators for an Adaptive DPE Algorithm: Comparative Study.

[BibT_eX]

[DOI]

Hussein Assaf

Proceedings of the IEEE International Conference on Artificial Intelligence Circuits and Systems, 2019

2018

Electronics and Packaging Intended for Emerging Harsh Environment Applications: A Review.

[BibT_eX]

[DOI]

Ahmad Hassan

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Fast, Single-Instruction-Multiple-Data, Scalable Priority Queue.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

A 1.5-pJ/bit, 9.04-Mbit/s Carrier-Width Demodulator for Data Transmission Over an Inductive Link Supporting Power and Data Transfer.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

Harvesting Energy From Aviation Data Lines: Implementation and Experimental Results.

[BibT_eX]

[DOI]

Maryam Mohajertehrani

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A pattern-based routing algorithm for a novel electronic system prototyping platform.

[BibT_eX]

[DOI]

Etienne Lepercq

Integr., 2018

Diagnosis algorithms for a reconfigurable and defect tolerant JTAG scan chain in large area integrated circuits.

[BibT_eX]

[DOI]

Integr., 2018

Enhanced Bloom filter utilisation scheme for string matching using a splitting approach.

[BibT_eX]

[DOI]

Naraig Manjikian

IET Commun., 2018

Formal Dependability Modeling and Optimization of Scrubbed-Partitioned TMR for SRAM-based FPGAs.

[BibT_eX]

[DOI]

CoRR, 2018

GaN Integration Technology, an Ideal Candidate for High-Temperature Applications: A Review.

[BibT_eX]

[DOI]

Ahmad Hassan

IEEE Access, 2018

New Insights Into Soft-Faults Induced Cardiac Pacemakers Malfunctions Analyzed at System-Level via Model Checking.

[BibT_eX]

[DOI]

IEEE Access, 2018

A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management.

[BibT_eX]

[DOI]

IEEE Access, 2018

Exploiting built-in delay lines for applying launch-on-capture at-speed testing on self-timed circuits.

[BibT_eX]

[DOI]

Proceedings of the 36th IEEE VLSI Test Symposium, 2018

HPQ: A High Capacity Hybrid Priority Queue Architecture for High-Speed Network Switches.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

Extending a CPU Cache for Efficient IPv6 Lookup.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Local Queueing-Based Data-Driven Task Scheduling for Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

Transport Triggered Polar Decoders.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018

A High-Efficiency Ultra-Low-Power CMOS Rectifier for RF Energy Harvesting Applications.

[BibT_eX]

[DOI]

Seyed Mohammad Noghabaei

Rafael L. Radin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Custom Low Power Processor for Polar Decoding.

[BibT_eX]

[DOI]

Mathieu Léonardon

Camille Leroux

David Binet

Christophe Jégo

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Implementation of a Cache-Based IPv6 Lookup System with Hashing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Design of a Low Latency 40 Gb/s Flow-Based Traffic Manager Using High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-Temperature Empirical Modeling for the I-V Characteristics of GaN150-Based HEMT.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

High-Temperature Modeling of the I-V Characteristics of GaN150 HEMT Using Machine Learning Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Vector Matrix Multiplication Using Crossbar Arrays: A Comparative Analysis.

[BibT_eX]

[DOI]

Hussein Assaf

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Reliability Analysis of the SPARC V8 Architecture via Fault Trees and UPPAL-SMC.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

A Low-Latency Memory-Efficient IPv6 Lookup Engine Implemented on FPGA Using High-Level Synthesis.

[BibT_eX]

[DOI]

Thibaut Stimpfling

Proceedings of the 18th IEEE/ACM International Symposium on Cluster, 2018

2017

Reliability Enhancement of Redundancy Management in AFDX Networks.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2017

Formal analysis of SEU mitigation for early dependability and performability analysis of FPGA-based space applications.

[BibT_eX]

[DOI]

J. Appl. Log., 2017

Formal Methods Based Synthesis of Single Event Transient Tolerant Combinational Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2017

Extensions to decision-tree based packet classification algorithms to address new classification paradigms.

[BibT_eX]

[DOI]

Comput. Networks, 2017

A DAQM-Based Load Balancing Scheme for High Performance Computing Platforms.

[BibT_eX]

[DOI]

IEEE Access, 2017

A 14.5 µW generic Carrier Width demodulator for telemetry-based Medical Devices.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A data driven CGRA Overlay Architecture with embedded processors.

[BibT_eX]

[DOI]

Himan Khanzadi

Jean-Pierre David

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Analysis of SEU propagation in sequential circuits at RTL using Satisfiability Modulo Theories.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Stability of GaN150-based HEMT in high temperature up to 400°C.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Improving performance of SCMA MPA decoders using estimation of conditional probabilities.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

FPGA implementation of Token-based Self-timed processors: A case study.

[BibT_eX]

[DOI]

Mickaël Fiorentino

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A high-speed traffic manager architecture for flow-based networking.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

Sub-ps resolution programmable delays implemented in a Xilinx FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

A Cache-Coherent Heterogeneous Architecture for Low Latency Real Time Applications.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

Scalable memory-less architecture for string matching with FPGAs.

[BibT_eX]

[DOI]

Ideh Sarbishei

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A multi-measurements RO-TDC implemented in a Xilinx field programmable gate array.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Comprehensive analysis of sequential circuits vulnerability to transient faults using SMT.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

An FPGA Coarse Grained Intermediate Fabric for Regular Expression Search.

[BibT_eX]

[DOI]

Thomas Luinaud

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Analysis of SEU Propagation in Combinational Circuits at RTL Based on Satisfiability Modulo Theories.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

An FPGA Overlay Architecture for Cost Effective Regular Expression Search (Abstract Only).

[BibT_eX]

[DOI]

Thomas Luinaud

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Joint power control and beamformer design with antenna selection.

[BibT_eX]

[DOI]

Faika Hoque

Christian Cardinal

Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016

Monitoring Thermal Stress in Wafer-Scale Integrated Circuits by the Attentive Vision Method Using an Infrared Camera.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2016

An Asynchronous Delta-Modulator Based A/D Converter for an Electronic System Prototyping Platform.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A novel spatially configurable differential interface for an electronic system prototyping platform.

[BibT_eX]

[DOI]

Integr., 2016

WeSPer: A flexible small delay defect quality metric.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Applying formal verification to early assessment of FPGA-based aerospace applications: Methodology and experience.

[BibT_eX]

[DOI]

Proceedings of the Annual IEEE Systems Conference, 2016

Quad-Level Carrier Width Modulation demodulator for micro-implants.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Towards LTE physical layer virtualization on a COTS multicore platform with efficient scheduling.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A fast systolic priority queue architecture for a flow-based Traffic Manager.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Performance characterization of an SCMA decoder.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

Towards efficient and concurrent FFTs implementation on Intel Xeon/MIC clusters for LTE and HPC.

[BibT_eX]

[DOI]

Mounir Khelifi

Daniel Massicotte

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A compact spatially configurable differential input stage for a field programmable interconnection network.

[BibT_eX]

[DOI]

Wasim Hussain

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Wireless power transfer through metallic barriers enclosing a harsh environment; feasibility and preliminary results.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Towards formal abstraction, modeling, and analysis of Single Event Transients at RTL.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A practical design method for prototyping self-timed processors using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Investigating the efficiency and accuracy of a data type reduction technique for soft error analysis.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Performance analysis of a reduced complexity SCMA decoder exploiting a low-complexity maximum-likelihood approximation.

[BibT_eX]

[DOI]

Roya Alizadeh

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Efficient and accurate analysis of single event transients propagation using SMT-based techniques.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Comprehensive non-functional analysis of combinational circuits vulnerability to single event transients.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Efficient probabilistic fault tree analysis of safety critical systems via probabilistic model checking.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

Detailed analysis of radiation-induced delays on I/O blocks of an SRAM-based FPGA.

[BibT_eX]

[DOI]

Fatima Zahra Tazi

Proceedings of the 2016 IEEE Canadian Conference on Electrical and Computer Engineering, 2016

Memory-Efficient String Matching for Intrusion Detection Systems using a High-Precision Pattern Grouping Algorithm.

[BibT_eX]

[DOI]

Bochra Boughzala

Proceedings of the 2016 Symposium on Architectures for Networking and Communications Systems, 2016

Efficient identification of Faces in video Streams using low-Power Multi-Core Devices.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Pattern Recognition and Computer Vision, 5th Ed., 2016

2015

An Interface for Open-Drain Bidirectional Communication in Field Programmable Interconnection Networks.

[BibT_eX]

[DOI]

Wasim Hussain

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Characterizing, modeling, and analyzing soft error propagation in asynchronous and synchronous digital circuits.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2015

Parallel independent FFT implementation on intel processors and Xeon phi for LTE and OFDM systems.

[BibT_eX]

[DOI]

Mounir Khelifi

Daniel Massicotte

Proceedings of the Nordic Circuits and Systems Conference, 2015

Self-timed circuits FPGA implementation flow.

[BibT_eX]

[DOI]

Mickaël Fiorentino

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

DPDK and MKL; Enabling technologies for near deterministic cloud-based signal processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Power-efficient hardware architecture for computing Split-Radix FFTs on highly sparsed spectrum.

[BibT_eX]

[DOI]

Hanieh Abdollahifakhr

François Gagnon

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Modeling the faulty behaviour of digital designs using a feed forward neural network approach.

[BibT_eX]

[DOI]

Zeynab Mirzadeh

Jean-François Boland

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Defect diagnosis algorithms for a field programmable interconnect network embedded in a Very Large Area Integrated Circuit.

[BibT_eX]

[DOI]

Gontran Sion

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Efficient multilevel formal analysis and estimation of design vulnerability to Single Event Transients.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

Harvesting energy from data lines for avionics applications: Power conversion chain architecture.

[BibT_eX]

[DOI]

Maryam Mohajertehrani

Umar Shafique

Proceedings of the 27th International Conference on Microelectronics, 2015

Towards an accurate reliability, availability and maintainability analysis approach for satellite systems based on probabilistic model checking.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Mapping applications on two-level configurable hardware.

[BibT_eX]

[DOI]

Himan Khanzadi

Jean-Pierre David

Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015

Design Intelligence for Interconnection Realization in Power-Managed SoCs.

[BibT_eX]

[DOI]

A. J. Al-Khalili

Proceedings of the Computational Intelligence in Digital and Network Designs and Applications, 2015

2014

Efficient Uniform Quantization Likelihood Evaluation for Particle Filters in Embedded Implementations.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2014

Optimizing the Parallel Tree-Search for Finding Shortest-Span Error-Correcting CDO Codes.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Determinism Enhancement of AFDX Networks via Frame Insertion and Sub-Virtual Link Aggregation.

[BibT_eX]

[DOI]

IEEE Trans. Ind. Informatics, 2014

A Configurable Multi-Rail Power and I/O Pad Applied to Wafer-Scale Systems.

[BibT_eX]

[DOI]

Nicolas Laflamme-Mayer

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A computationally efficient importance sampling tracking algorithm.

[BibT_eX]

[DOI]

Rana Farah

Guillaume-Alexandre Bilodeau

Mach. Vis. Appl., 2014

A Parallel Systematic Resampling Algorithm for High-Speed Particle Filters in Embedded Systems.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

On Delay Faults Affecting I/O Blocks of an SRAM-Based FPGA Due to Ionizing Radiations.

[BibT_eX]

[DOI]

CoRR, 2014

A Hausdorff Heuristic for Efficient Computation of Graph Edit Distance.

[BibT_eX]

[DOI]

Proceedings of the Structural, Syntactic, and Statistical Pattern Recognition, 2014

A current-output DAC for low-power low-noise log-domain ΔΣ modulators.

[BibT_eX]

[DOI]

Mohamed A. Shaheen

Anas A. Hamoui

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

A memory transaction model for Sparse Matrix-Vector multiplications on GPUs.

[BibT_eX]

[DOI]

Thalie Keklikian

Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 23rd North Atlantic Test Workshop, 2014

Adaptive real-time DSP acceleration for SoC applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Modeling, analyzing, and abstracting single event transient propagation at gate level.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Probabilistic model checking based DAL analysis to optimize a combined TMR-blind-scrubbing mitigation technique for FPGA-based aerospace applications.

[BibT_eX]

[DOI]

Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Vt-conscious repeater insertion in power-managed VLSI.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Abstracting Single Event Transient characteristics variations due to input patterns and fan-out.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Design and validation of a novel reconfigurable and defect tolerant JTAG scan chain.

[BibT_eX]

[DOI]

Yan Basile-Bellavance

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Neuromuscular Representation and Synthetic Generation of Handwritten Whiteboard Notes.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Frontiers in Handwriting Recognition, 2014

A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Probabilistic model checking of single event transient propagation at RTL level.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Constraint-based configuration complexity model for autonomic network configuration management.

[BibT_eX]

[DOI]

Rudy Deca

Omar Cherkaoui

Proceedings of the Global Information Infrastructure and Networking Symposium, 2014

2013

Efficient Parallel Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2013

A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design.

[BibT_eX]

[DOI]

J. Electron. Test., 2013

A 2D Gaussian smoothing kernel mapped to heterogeneous platforms.

[BibT_eX]

[DOI]

Abdelaziz Trabelsi

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A methodology for system-level fault injection based on gate-level faulty behavior.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A netlist pruning tool for an electronic system prototyping platform.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A reformulated systematic resampling algorithm for particle filters and its parallel implementation in an application-specific instruction-set processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

An interface for the I<sup>2</sup>C protocol in the WaferBoard™.

[BibT_eX]

[DOI]

Wasim Hussain

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A spatiotemporal attention operator for monitoring thermo-mechanical stress in wafer-scale integrated circuits using an infrared camera.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis, 2013

Optimal packet classification applicable tothe OpenFlow context.

[BibT_eX]

[DOI]

Proceedings of the first edition workshop on High performance and programmable networking, 2013

Early Analysis of Soft Error Effects for Aerospace Applications Using Probabilistic Model Checking.

[BibT_eX]

[DOI]

Proceedings of the Formal Techniques for Safety-Critical Systems, 2013

Accelerating a modified Gaussian pyramid with a customized processor.

[BibT_eX]

[DOI]

Diana Carolina Gil

Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Software rendering methods to display wafer scale integrated circuit dataset.

[BibT_eX]

[DOI]

Mikael Guillemot

Proceedings of the 26th IEEE Canadian Conference on Electrical and Computer Engineering CCECE 2013, 2013

2012

Postsilicon Tuning of Standby Supply Voltage in SRAMs to Reduce Yield Losses Due to Parametric Data-Retention Failures.

[BibT_eX]

[DOI]

Afshin Nourivand

IEEE Trans. Very Large Scale Integr. Syst., 2012

Loop Acceleration Exploration for ASIP Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2012

Real-Time Computation of Local Neighborhood Functions in Application-Specific Instruction-Set Processors.

[BibT_eX]

[DOI]

P. Aubertin

IEEE Trans. Very Large Scale Integr. Syst., 2012

Efficient Search Algorithm for Determining Optimal R=1/2 Systematic Convolutional Self-Doubly Orthogonal Codes.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 2012

A High-Efficiency Low-Voltage CMOS Rectifier for Harvesting Energy in Implantable Devices.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2012

Rule-Based Network Service Provisioning.

[BibT_eX]

[DOI]

Rudy Deca

Omar Cherkaoui

J. Networks, 2012

System modeling and multicore simulation using transactions.

[BibT_eX]

[DOI]

Amine Anane

Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

A new approach for pin detection for an electronic system prototyping reconfigurable platform.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

An FPGA compatible asynchronous wake-up receiver for Wireless Sensor Networks.

[BibT_eX]

[DOI]

Jean-François Pons

Jean-Jules Brault

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Probabilistic model checking of clock domain crossing interfaces.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International NEWCAS Conference, 2012

State-holding free NULL Convention Logic™.

[BibT_eX]

[DOI]

Jean-François Pons

Jean-Jules Brault

Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Propagating analog signals through a fully digital network on an electronic system prototyping platform.

[BibT_eX]

[DOI]

Walder Andre

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Identification of soft error glitch-propagation paths: Leveraging SAT solvers.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Two-level configuration for FPGA: A new design methodology based on a computing fabric.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A novel hybrid FIFO asynchronous clock domain crossing interfacing method.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Optimal scheduling policy for AFDX End-Systems with virtual links of identical bandwidth allocation gap size.

[BibT_eX]

[DOI]

Romain Nishi

Guchuan Zhu

Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011

A Laser-Trimmed Rail-to-Rail Precision CMOS Operational Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2011

A Low-Power Asynchronous Step-Down DC-DC Converter for Implantable Devices.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2011

All digital skew tolerant synchronous interfacing methods for high-performance point-to-point communications in deep sub-micron SoCs.

[BibT_eX]

[DOI]

Integr., 2011

Analysis of Resistive Open Defects in Drowsy SRAM Cells.

[BibT_eX]

[DOI]

Afshin Nourivand

J. Electron. Test., 2011

Comparative analysis of contrast enhancement algorithms in surveillance imaging.

[BibT_eX]

[DOI]

Diana Carolina Gil

Rana Farah

Guillaume-Alexandre Bilodeau

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Activity management in battery-powered embedded systems: A case study of ZigBee® WSN.

[BibT_eX]

[DOI]

A. J. Al-Khalili

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Customized embedded processor design for global photographic tone mapping.

[BibT_eX]

[DOI]

Diana Carolina Gil

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A GPGPU-based software implementation of the PBDI deinterlacing algorithm.

[BibT_eX]

[DOI]

Gilbert Kowarzyk

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

SEGP-Finder: Tool for identification of Soft Error Glitch-Propagating paths at gate level.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

A tracking algorithm suitable for embedded systems implementation.

[BibT_eX]

[DOI]

Rana Farah

Guillaume-Alexandre Bilodeau

Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

Repeater insertion in power-managed VLSI systems.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Modeling R-2R Segmented-Ladder DACs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Crosstalk-Glitch Gating: A Solution for Designing Glitch-Tolerant Asynchronous Handshake Interface Mechanisms for GALS Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

Crosstalk Glitch Propagation Modeling for Asynchronous Interfaces in Globally Asynchronous Locally Synchronous Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2010

An interconnect-aware Dynamic Voltage Scaling scheme for DSM VLSI.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Fully integrated ultra-low-power asynchronously driven step-down DC-DC converter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

A spatially reconfigurable fast differential interface for a wafer scale configurable platform.

[BibT_eX]

[DOI]

Olivier Valorge

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Thermo-mechanical analysis of a reconfigurable wafer-scale integrated circuit.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2009

An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs.

[BibT_eX]

[DOI]

Yves Gagnon

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

A very-high output impedance charge pump for low-voltage low-power PLLs.

[BibT_eX]

[DOI]

Louis-François Tanguay

Microelectron. J., 2009

A novel low-drop CMOS active rectifier for RF-powered devices: Experimental results.

[BibT_eX]

[DOI]

Microelectron. J., 2009

A low-power 2GHz data conversion using delta modulation for portable application.

[BibT_eX]

[DOI]

Integr., 2009

Workflow for an Electronic Configurable Prototyping System.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

An All-digital Skew-adaptive Clock Scheduling Algorithm for Heterogeneous Multiprocessor Systems on Chips (MPSoCs).

[BibT_eX]

[DOI]

Syed Rafay Hasan

Bill Pontikakis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Estimation of energy performance in computing platforms.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

A low-area power-efficient CMOS active rectifier for wirelessly powered medical devices.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

An interconnect-aware delay model for dynamic voltage scaling in NM technologies.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Guest Editorial: 20 Years of ASAP.

[BibT_eX]

[DOI]

Wayne Luk

Oskar Mencer

J. Signal Process. Syst., 2008

Spur Model for a Fixed-Frequency Signal Subject to Periodic Jitter.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2008

On the Design of Undersampling Continuous-Time Bandpass Delta-Sigma Modulators for Gigahertz Frequency A/D Conversion.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Laser Fine-Tuneable Deep-Submicrometer CMOS 14-bit DAC.

[BibT_eX]

[DOI]

Yves Gagnon

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Design of a High-Speed Differential Frequency-to-Voltage Converter and Its Application in a 5-GHz Frequency-Locked Loop.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2008

Modeling and simulation of complex heterogeneous systems.

[BibT_eX]

[DOI]

Amine Anane

Julie Vachon

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Digital signal propagation on a wafer-scale smart active programmable interconnect.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Hardware/software system co-verification of an active reconfigurable board with SystemC-VHDL.

[BibT_eX]

[DOI]

Yan Basile-Bellavance

Etienne Lepercq

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Loop-oriented metrics for exploring an application-specific architecture design-space.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Conference on Application-Specific Systems, 2008

A very-high output impedance current mirror for very-low voltage biomedical analog circuits.

[BibT_eX]

[DOI]

Louis-François Tanguay

Hossein Mahvash Mohammadi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Novel Application-specific Instruction-set Processor Design Approach for Video Processing Acceleration.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

A Five-Field Motion Compensated Deinterlacing Method Based on Vertical Motion.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2007

A high-level requirements engineering methodology for electronic system-level design.

[BibT_eX]

[DOI]

Nicolas Gorse

P. Bélanger

Alexandre Chureau

Comput. Electr. Eng., 2007

Constraint-based model for network service provisioning.

[BibT_eX]

[DOI]

Ann. des Télécommunications, 2007

Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS Amplifier.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS Technology.

[BibT_eX]

[DOI]

Syed Rafay Hasan

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

High-Voltage DMOS Integrated Circuits with Floating Gate Protection Technique.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Modeling the Substrate Noise Injected by a DC-DC Converter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Signal Integrity Analysis of a High Precision D/A Converter.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Iterative Noise-Compensated Method to Improve LPC Based Speech Analysis.

[BibT_eX]

[DOI]

Abdelaziz Trabelsi

Mounir Boukadoum

Proceedings of the 14th IEEE International Conference on Electronics, 2007

An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Digital Measurement Technique for Capacitance Variation Detection on Integrated Circuit I/Os.

[BibT_eX]

[DOI]

Jaouad El Fouladi

Proceedings of the 14th IEEE International Conference on Electronics, 2007

A Methodology to Evaluate the Energy Efficiency of Application Specific Processors.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

New Analog Test Metrics Based on Probabilistic and Deterministic Combination Approaches.

[BibT_eX]

[DOI]

Abdessatar Abderrahman

Abdelhakim Khouas

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

A Metric for Automatic Word-Length Determination of Hardware Datapaths.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

Validation by Fault Injection of a Software Error Detection Technique Dealing with Critical Single Event Upsets.

[BibT_eX]

S. Torrellas

Bogdan Nicolescu

Raul Velazco

Mario García-Valderas

Proceedings of the 7th Latin American Test Workshop, 2006

Zero skew differential clock distribution network.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 0.8V algorithmically defined buffer and ring oscillator low-energy design for nanometer SoCs.

[BibT_eX]

[DOI]

Bill Pontikakis

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel 2-GHz band-pass delta modulator dedicated to wireless receivers.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Design exploration with an application-specific instruction-set processor for ELA deinterlacing.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

High-voltage operational amplifier based on dual floating-gate transistors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A power planning model for implantable stimulators.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Architecture of a hypertransport tunnel.

[BibT_eX]

[DOI]

Ami Castonguay

Hossein Mahvash Mohammadi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A Threshold-Based Deinterlacing Algorithm Using Motion Compensation and Directional Interpolation.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Electronics, 2006

High speed differential pulse-width control loop based on frequency-to-voltage converters.

[BibT_eX]

[DOI]

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Evaluation of a Software-Based Error Detection Technique by RT-Level Fault Injection.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Soft-error classification and impact analysis on real-time operating systems.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Design of an Active-RC Bandpass Filter for a Subsampling RF Delta Modulator.

[BibT_eX]

[DOI]

Proceedings of the Canadian Conference on Electrical and Computer Engineering, 2006

2005

Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.

[BibT_eX]

[DOI]

Ismaïl Chabini

ACM Trans. Design Autom. Electr. Syst., 2005

A system level implementation strategy and partitioning heuristic for LUT-based applications.

[BibT_eX]

[DOI]

Hakim Khali

Jean-Louis Houle

Comput. Electr. Eng., 2005

A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC.

[BibT_eX]

[DOI]

Ami Castonguay

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Performance Improvement of Configurable Processor Architectures Using a Variable Clock Period.

[BibT_eX]

[DOI]

Bill Pontikakis

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Component-Based Methodology for Hardware Design of a Dataflow Processing Network.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

A Generic Method for Embedded Measurement and Compensation of Process and Temperature Variations in SoCs.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

Analysis of Wave-Pipelined Domino Logic Circuit and Clocking Styles Subject to Parametric Variations.

[BibT_eX]

[DOI]

Wei Ling

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Characterization of laser-induced photoexcitation effect on a surrounding CMOS ring oscillator.

[BibT_eX]

[DOI]

Guillaume Wild

Michel Meunier

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A complete spurs distribution model for direct digital period synthesizers.

[BibT_eX]

[DOI]

Max-Elie Salomon

Abdelhakim Khouas

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design methods for CMOS low-current finely tunable voltage references covering a wide output range.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fast parameters optimization of an iterative decoder using a configurable hardware accelerator.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Application specific instruction-set processor generation for video processing based on loop optimization.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

. A new switch compensation technique for inverted R-2R ladder DACs.

[BibT_eX]

[DOI]

Yves Gagnon

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms.

[BibT_eX]

[DOI]

Alexandre Landry

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Implementation of a cycle by cycle variable speed processor.

[BibT_eX]

[DOI]

H. G. Epassa

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel approach for implementing ultra-high speed flash ADC using MCML circuits.

[BibT_eX]

[DOI]

Dinh Hung Dang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Parameters estimation applied to automatic video processing algorithms validation.

[BibT_eX]

[DOI]

S. Catudal

Marc-André Cantin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Modeling power budget requirements of implantable electronic devices.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Conference on Electronics, 2005

Gate oxide protection in HV CMOS/DMOS integrated circuits: Design and experimental results.

[BibT_eX]

[DOI]

Robert Chebli

Proceedings of the 12th IEEE International Conference on Electronics, 2005

The Role of Model-Level Transactors and UML in Functional Prototyping of Systems-on-Chip: A Software-Radio Application.

[BibT_eX]

[DOI]

Alexandre Chureau

Proceedings of the 2005 Design, 2005

2004

A Unified Environment to Assess Image Quality in Video Processing.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

Multi-processor SoC integration: a case study on BlueGene/L.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models.

[BibT_eX]

[DOI]

S. Regimbal

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

A Customizable Embedded SoC Platform Architecture.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters.

[BibT_eX]

[DOI]

D. Morin

Frédéric Normandin

Marie-Eve Grandmaison

H. Dang

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

A Framework for Implementing Reusable Digital Signal Processing Modules.

[BibT_eX]

[DOI]

L.-P. Lafrance

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Interface-based Design of Systems-on-Chip using UML-RT.

[BibT_eX]

[DOI]

Alexandre Chureau

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

Assertion-based on-line verification and debug environment for complex hardware systems.

[BibT_eX]

Kevin Peterson

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Spurs modeling in direct digital period synthesizers related to phase accumulator truncation.

[BibT_eX]

[DOI]

Badre Izouggaghen

Abdelhakim Khouas

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An on-chip delay measurements module for nanostructures characterization.

[BibT_eX]

Olivier Duval

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

An ADPLL circuit using a DDPS for genlock applications.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Shunt-peaking in MCML gates and its application in the design of a 20 Gb/s half-rate phase detector.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Performance Evaluation and Failure Rate Prediction for the Soft Implemented Error Detection Technique.

[BibT_eX]

[DOI]

Bogdan Nicolescu

Raoul Velazco

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

The Effect of p-Coupling on the Electronic Properties of 1, 4-Dithiol Benzene Stacking.

[BibT_eX]

[DOI]

Mohammed Layachi

Alain Rochefort

Proceedings of the 2004 International Conference on MEMS, 2004

An Integrated Test Platform for Nanostructure Electrical Characterization.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on MEMS, 2004

2003

Improvement of sensor accuracy in the case of a variable surface reflectance gradient for active laser range finders.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2003

Methods for minimizing dynamic power consumption in synchronous designs with multiple supply voltages.

[BibT_eX]

[DOI]

Ismaïl Chabini

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

A Pattern Reordering Approach Based on Ambiguity Detection for Online Category Learning.

[BibT_eX]

[DOI]

Eric Granger

IEEE Trans. Pattern Anal. Mach. Intell., 2003

Automating Functional Coverage Analysis Based on an Executable Specification.

[BibT_eX]

[DOI]

A. Baron

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

SoC platform architecture for a network processor.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on System-on-Chip, 2003

A new memory reference reduction method for FFT implementation on DSP.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A CMOS three-state frequency detector complementary to an enhanced linear phase detector for PLL, DLL or high frequency clock skew measurement.

[BibT_eX]

[DOI]

Mathieu Renaud

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A hardware-software co-design model for real-time 3D image computation using active laser range finders: a case study.

[BibT_eX]

[DOI]

Hakim Khali

Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.

[BibT_eX]

[DOI]

Ismaïl Chabini

Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

SIED: Software Implemented Error Detection.

[BibT_eX]

[DOI]

Bogdan Nicolescu

Raoul Velazco

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Efficiency of Transient Bit-Flips Detection by Software Means: A Complete Study.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

IEEE 1149.1 Based Defect and Fault Tolerant Scan Chain for Wafer Scale Integration.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

A practical approach to model long MIS interconnects in VLSI circuits.

[BibT_eX]

[DOI]

Zhong-Fang Jin

Jean-Jacques Laurin

IEEE Trans. Very Large Scale Integr. Syst., 2002

A direct digital period synthesis circuit.

[BibT_eX]

[DOI]

Dorin Emil Calbaza

IEEE J. Solid State Circuits, 2002

FPGA Implementation of a Sub-pixel Correction Algorithm for Active Laser Range Finders.

[BibT_eX]

[DOI]

Hakim Khali

Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2002), 2002

A linear phase detector for arbitrary clock signals.

[BibT_eX]

[DOI]

Mathieu Renaud

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Architecture and performance characterization of hardware and software implementations of the Crozier frequency estimation algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A CMOS phase-locked loop with an auto-calibrated VCO.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique.

[BibT_eX]

[DOI]

A. Bendali

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2002

Yield Modeling of a WSI Telecom Router Architecture.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

2001

Optimal design of synchronous circuits using software pipelining techniques.

[BibT_eX]

[DOI]

Michel Boyer

ACM Trans. Design Autom. Electr. Syst., 2001

Direct digital frequency synthesis of low-jitter clocks.

[BibT_eX]

[DOI]

Dorin Emil Calbaza

IEEE J. Solid State Circuits, 2001

Tools for the Characterization of Bipolar CML Testability.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Methods for optimizing register placement in synchronous circuits derived using software pipelining techniques.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Performance estimators for hardware/software co-design.

[BibT_eX]

[DOI]

Lévis Thériault

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Minimizing process-induced skew using delay tuning.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

A new controlled gain phase-locked loop technique.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

An automatic word length determination method.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Determining Schedules for Reducing Power Consumption Using Multiple Supply Voltages.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

A methodology for validating digital circuits with mutation testing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A new fully integrated CMOS phase-locked loop with low jitter and fast lock time.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Analysis of quantization effects in a digital hardware implementation of a fuzzy ART neural network algorithm.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Very short locking time PLL based on controlled gain technique.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

An efficient verification method for a class of multi-phase sequential circuits.

[BibT_eX]

[DOI]

Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000

A method to derive application-specific embedded processing cores.

[BibT_eX]

[DOI]

Olivier Hébert

Ivan C. Kraljic

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Reconfigurable pipelined 2-D convolvers for fast digital signal processing.

[BibT_eX]

[DOI]

B. Bosi

IEEE Trans. Very Large Scale Integr. Syst., 1999

Generalization, discrimination, and multiple categorization using adaptive resonance theory.

[BibT_eX]

[DOI]

Jean-François Crespo

IEEE Trans. Neural Networks, 1999

Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 1999

A new approach to analyze interconnect delays in RC wire models.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Development of a high performance TSPC library for implementation of large digital building blocks.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Jitter model of direct digital synthesis clock generators.

[BibT_eX]

[DOI]

Dorin Emil Calbaza

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of a JTAG Based Run Time Reconfigurable System.

[BibT_eX]

[DOI]

Cynthia Cousineau

François Laperle

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

Design For Testability Method for CML Digital Circuits.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

1998

A comparison of self-organizing neural networks for fast clustering of radar pulses.

[BibT_eX]

[DOI]

Signal Process., 1998

Parallel ultra large scale engine SIMD architecture for real-time digital signal processing applications.

[BibT_eX]

[DOI]

Paul Marriott

Ivan C. Kraljic

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Optimal design of synchronous circuits using software pipelining techniques.

[BibT_eX]

[DOI]

Imed Eddine Bennour

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Design of Clock Distribution Networks in Presence of Process Variations.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

A Comparative Analysis of Fuzzy ART Neural Network Implementations: The Advantages of Reconfigurable Computing.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

Reducing Fault Sensitivity of Microprocessor-Based Systems by Modifying Workload Structure.

[BibT_eX]

[DOI]

Steve Masson

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997

Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

Multiple categorization using fuzzy ART.

[BibT_eX]

[DOI]

Jean-François Crespo

Proceedings of International Conference on Neural Networks (ICNN'97), 1997

A Cost Model for VLSI / MCM Systems.

[BibT_eX]

[DOI]

Michel Kafrouni

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Are defect-tolerant circuits with redundancy really cost-effective? Complete and realistic cost model.

[BibT_eX]

[DOI]

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

Timing analysis speed-up using a hierarchical and a multimode approach.

[BibT_eX]

[DOI]

Michel R. Dagenais

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Reconstruction method for jitter tolerant data acquisition system.

[BibT_eX]

[DOI]

J. Electron. Test., 1996

Panel Summaries.

[BibT_eX]

IEEE Des. Test Comput., 1996

Design and performance of CMOS TSPC cells for high speed pseudo random testing.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Implementing Fault Injection and Tolerance Mechanisms in Multiprocessor Systems.

[BibT_eX]

[DOI]

N. Gagnon

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

Bounds on the performance of partial selection networks.

[BibT_eX]

[DOI]

IEEE Trans. Commun., 1995

Equivalence Proofs of Some Yield Modeling Methods for Defect-Tolerant Integrated Circuits.

[BibT_eX]

[DOI]

Jean-Louis Houle

IEEE Trans. Computers, 1995

Producing Reliable Initialization and Test of Sequential Circuits with Pseudorandom Vectors.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1995

On the design of at-speed testable VLSI circuits.

[BibT_eX]

[DOI]

Mohamed Soufi

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

On Using Partial Reset for Pseudo-Random Testing.

[BibT_eX]

[DOI]

Mohamed Soufi

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Cost analysis of a new algorithmic-based soft-error tolerant architecture.

[BibT_eX]

[DOI]

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

A new method for testing mixed analog and digital circuits.

[BibT_eX]

[DOI]

Janusz Rzeszut

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995

1994

Pipelining communications in large VLSI/ULSI systems.

[BibT_eX]

[DOI]

N. Arel

IEEE Trans. Very Large Scale Integr. Syst., 1994

A systolic architecture for fast stack sequential decoders.

[BibT_eX]

[DOI]

David Haccoun

IEEE Trans. Commun., 1994

A multiprocessor architecture for multiple path stack sequential decoders.

[BibT_eX]

[DOI]

David Haccoun

IEEE Trans. Commun., 1994

A Fast Method to Evaluate the Optimum Number of Spares in Defect-Tolerant Integrated Circuits.

[BibT_eX]

[DOI]

Jean-Louis Houle

IEEE Trans. Computers, 1994

A Fast CMOS Voltage-Controlled Ring Oscillator.

[BibT_eX]

[DOI]

Dmitri Chtchvyrkov

John F. Currie

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Fast Low-Power Driver for Long Interconnections in VLSI Systems.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Pseudo-Random Vector Compaction for Sequential Testability.

[BibT_eX]

[DOI]

Naim Ben-Hamida

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A Comparative Study of Single-Phase Clocked Latches Using Estimation Criteria.

[BibT_eX]

[DOI]

Sameh Ghannoum

Dmitri Chtchvyrkov

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Fast Convergence with Low Precision Weights in ART1 Networks.

[BibT_eX]

[DOI]

Jean-François Crespo

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Estimation of Simultaneous Switching Power and Ground Noise of Static CMOS Combinational Circuits.

[BibT_eX]

[DOI]

Abdessatar Abderrahman

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Defect and Fault Tolerant Scan Chains.

[BibT_eX]

Rachid Kermouche

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.

[BibT_eX]