Yvan Tortorella

According to our database, Yvan Tortorella authored at least 11 papers between 2022 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

A Heterogeneous RISC-V Based SoC for Secure Nano-UAV Navigation.

Luca Valente, Alessandro Nadalini, Asif Hussain Chiralil Veeran, Mattia Sinigaglia, Bruno Sá, Nils Wistoff, Yvan Tortorella, Simone Benatti, Rafail Psiakis, Ari Kulmala, Baker Mohammad, Sandro Pinto, Daniele Palossi, Luca Benini, Davide Rossi

IEEE Trans. Circuits Syst. I Regul. Pap., May, 2024

A Flexible Template for Edge Generative AI with High-Accuracy Accelerated Softmax & GELU.

Andrea Belano, Yvan Tortorella, Angelo Garofalo, Luca Benini, Davide Rossi, Francesco Conti

CoRR, 2024

2023

RedMule: A mixed-precision matrix-matrix operation engine for flexible and energy-efficient on-chip linear algebra and TinyML training acceleration.

Yvan Tortorella, Luca Bertaccini, Luca Benini, Davide Rossi, Francesco Conti

Future Gener. Comput. Syst., December, 2023

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training.

Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti

CoRR, 2023

Hybrid Modular Redundancy: Exploring Modular Redundancy Approaches in RISC-V Multi-Core Computing Clusters for Reliable Processing in Space.

Michael Rogenmoser, Yvan Tortorella, Davide Rossi, Francesco Conti, Luca Benini

CoRR, 2023

RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project.

William Fornaciari, Federico Reghenzani, Giovanni Agosta, Davide Zoni, Andrea Galimberti, Francesco Conti, Yvan Tortorella, Emanuele Parisi, Francesco Barchi, Andrea Bartolini, Andrea Acquaviva, Daniele Gregori, Salvatore Cognetta, Carlo Ciancarelli, Antonio Leboffe, Paolo Serri, Alessio Burrello, Daniele Jahier Pagliari, Gianvito Urgese, Maurizio Martina, Guido Masera, Rosario Di Carlo, Antonio Sciarappa

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Shaheen: An Open, Secure, and Scalable RV64 SoC for Autonomous Nano-UAVs.

Luca Valente, Asif Veeran, Mattia Sinigaglia, Yvan Tortorella, Alessandro Nadalini, Nils Wistoff, Bruno Sá, Angelo Garofalo, Rafail Psiakis, M. Tolba, Ari Kulmala, Nimisha Limaye, Ozgur Sinanoglu, Sandro Pinto, Daniele Palossi, Luca Benini, Baker Mohammad, Davide Rossi

Proceedings of the 35th IEEE Hot Chips Symposium, 2023

PULP Fiction No More - Dependable PULP Systems for Space.

Markus Ulbricht, Yvan Tortorella, Michael Rogenmoser, Li Lu, Junchao Chen, Francesco Conti, Milos Krstic, Luca Benini

Proceedings of the IEEE European Test Symposium, 2023

HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoC.

Luca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training.

Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

RedMulE: A Compact FP16 Matrix-Multiplication Accelerator for Adaptive Deep Learning on RISC-V-Based Ultra-Low-Power SoCs.

Yvan Tortorella, Luca Bertaccini, Davide Rossi, Luca Benini, Francesco Conti

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022