Yuzong Chen

Orcid: 0000-0001-6387-327X

Affiliations:
  • Cornell University, Department of Electrical and Computer Engineering, Ithaca, NY, USA


According to our database1, Yuzong Chen authored at least 14 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Kratos: An FPGA Benchmark for Unrolled DNNs with Fine-Grained Sparsity and Mixed Precision.
CoRR, 2024

Learning from Students: Applying t-Distributions to Explore Accurate and Efficient Formats for LLMs.
CoRR, 2024

2023
BP-SCIM: A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

M4BRAM: Mixed-Precision Matrix-Matrix Multiplication in FPGA Block RAMs.
Proceedings of the International Conference on Field Programmable Technology, 2023

BRAMAC: Compute-in-BRAM Architectures for Multiply-Accumulate on FPGAs.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
An Overview of Processing-in-Memory Circuits for Artificial Intelligence and Machine Learning.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A 181µW Real-Time 3-D Hand Gesture Recognition System based on Bi-directional Convolution and Computing-Efficient Feature Clustering.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
A Reconfigurable 4T2R ReRAM Computing In-Memory Macro for Efficient Edge Applications.
IEEE Open J. Circuits Syst., 2021

AND8T SRAM Macro with Improved Linearity for Multi-Bit In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Configurable Randomness Enhanced RRAM PUF with Biased Current Sensing Scheme.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A Multi-Functional 4T2R ReRAM Macro Enabling 2-Dimensional Access and Computing In-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
Reconfigurable 2T2R ReRAM Architecture for Versatile Data Storage and Computing In-Memory.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Reconfigurable 2T2R ReRAM with Split Word-Lines for TCAM Operation and In-Memory Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020


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