Yuze Chi

According to our database, Yuze Chi authored at least 36 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs.

Moazin Khatti, Xingyu Tian, Ahmad Sedigh Baroughi, Akhil Raj Baranwal, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang

ACM Trans. Reconfigurable Technol. Syst., September, 2024

RapidStream IR: Infrastructure for FPGA High-Level Physical Synthesis.

Jason Lau, Yuanlong Xiao, Yutong Xie, Yuze Chi, Linghao Song, Shaojie Xiang, Michael Lo, Zhiru Zhang, Jason Cong, Licheng Guo

CoRR, 2024

TAPA-CS: Enabling Scalable Accelerator Design on Distributed HBM-FPGAs.

Neha Prakriya, Yuze Chi, Suhail Basalama, Linghao Song, Jason Cong

Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023

RapidStream 2.0: Automated Parallel Implementation of Latency-Insensitive FPGA Designs Through Partial Reconfiguration.

Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Eddie Hung, Wuxi Li, Jason Lau, Weikang Qiao, Yuze Chi, Linghao Song, Yuanlong Xiao, Alireza Kaviani, Zhiru Zhang, Jason Cong

ACM Trans. Reconfigurable Technol. Syst., December, 2023

TAPA: A Scalable Task-parallel Dataflow Programming Framework for Modern FPGAs with Co-optimization of HLS and Physical Design.

Licheng Guo, Yuze Chi, Jason Lau, Linghao Song, Xingyu Tian, Moazin Khatti, Weikang Qiao, Jie Wang, Ecenur Ustun, Zhenman Fang, Zhiru Zhang, Jason Cong

ACM Trans. Reconfigurable Technol. Syst., December, 2023

TARO: Automatic Optimization for Free-Running Kernels in FPGA High-Level Synthesis.

Young Kyu Choi, Yuze Chi, Jason Lau, Jason Cong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023

SASA: A Scalable and Automatic Stencil Acceleration Framework for Optimized Hybrid Spatial and Temporal Parallelism on HBM-based FPGAs.

Xingyu Tian, Zhifan Ye, Alec Lu, Licheng Guo, Yuze Chi, Zhenman Fang

ACM Trans. Reconfigurable Technol. Syst., June, 2023

Democratizing Domain-Specific Computing.

Yuze Chi, Weikang Qiao, Atefeh Sohrabizadeh, Jie Wang, Jason Cong

Commun. ACM, 2023

Callipepla: Stream Centric Instruction Set and Mixed Precision for Accelerating Conjugate Gradient Solver.

Linghao Song, Licheng Guo, Suhail Basalama, Yuze Chi, Robert F. Lucas, Jason Cong

Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2023

PASTA: Programming and Automation Support for Scalable Task-Parallel HLS Programs on Modern Multi-Die FPGAs.

Moazin Khatti, Xingyu Tian, Yuze Chi, Licheng Guo, Jason Cong, Zhenman Fang

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022

PYXIS: An Open-Source Performance Dataset Of Sparse Accelerators.

Linghao Song, Yuze Chi, Jason Cong

Proceedings of the IEEE International Conference on Acoustics, 2022

Sextans: A Streaming Accelerator for General-Purpose Sparse-Matrix Dense-Matrix Multiplication.

Linghao Song, Yuze Chi, Atefeh Sohrabizadeh, Young-kyu Choi, Jason Lau, Jason Cong

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

SPA-GCN: Efficient and Flexible GCN Accelerator with Application for Graph Similarity Computation.

Atefeh Sohrabizadeh, Yuze Chi, Jason Cong

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

RapidStream: Parallel Physical Implementation of FPGA HLS Designs.

Licheng Guo, Pongstorn Maidee, Yun Zhou, Chris Lavin, Jie Wang, Yuze Chi, Weikang Qiao, Alireza Kaviani, Zhiru Zhang, Jason Cong

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Accelerating SSSP for Power-Law Graphs.

Yuze Chi, Licheng Guo, Jason Cong

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplication.

Linghao Song, Yuze Chi, Licheng Guo, Jason Cong

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

StreamGCN: Accelerating Graph Convolutional Networks with Streaming Processing.

Atefeh Sohrabizadeh, Yuze Chi, Jason Cong

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021

Design Automation and Optimization for Memory-Bound Application Accelerators.

Yuze Chi

PhD thesis, 2021

SPA-GCN: Efficient and Flexible GCN Accelerator with an Application for Graph Similarity Computation.

Atefeh Sohrabizadeh, Yuze Chi, Jason Cong

CoRR, 2021

AutoBridge: Coupling Coarse-Grained Floorplanning and Pipelining for High-Frequency HLS Design on Multi-Die FPGAs.

Licheng Guo, Yuze Chi, Jie Wang, Jason Lau, Weikang Qiao, Ecenur Ustun, Zhiru Zhang, Jason Cong

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

HBM Connect: High-Performance HLS Interconnect for FPGA HBM.

Young-kyu Choi, Yuze Chi, Weikang Qiao, Nikola Samardzic, Jason Cong

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Extending High-Level Synthesis for Task-Parallel Programs.

Yuze Chi, Licheng Guo, Young-kyu Choi, Jie Wang, Jason Cong

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Extending High-Level Synthesis for Task-Parallel Programs.

Yuze Chi, Licheng Guo, Jason Lau, Young-kyu Choi, Jie Wang, Jason Cong

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020

FLASH: Fast, Parallel, and Accurate Simulator for HLS.

Young-kyu Choi, Yuze Chi, Jie Wang, Jason Cong

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

When HLS Meets FPGA HBM: Benchmarking and Bandwidth Optimization.

Young-kyu Choi, Yuze Chi, Jie Wang, Licheng Guo, Jason Cong

CoRR, 2020

HeteroHalide: From Image Processing DSL to Efficient FPGA Acceleration.

Jiajie Li, Yuze Chi, Jason Cong

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency.

Licheng Guo, Jason Lau, Yuze Chi, Jie Wang, Cody Hao Yu, Zhe Chen, Zhiru Zhang, Jason Cong

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Exploiting Computation Reuse for Stencil Accelerators.

Yuze Chi, Jason Cong

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing.

Guohao Dai, Tianhao Huang, Yuze Chi, Jishen Zhao, Guangyu Sun, Yongpan Liu, Yu Wang, Yuan Xie, Huazhong Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing.

Yi-Hsiang Lai, Yuze Chi, Yuwei Hu, Jie Wang, Cody Hao Yu, Yuan Zhou, Jason Cong, Zhiru Zhang

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

Rapid Cycle-Accurate Simulator for High-Level Synthesis.

Yuze Chi, Young-kyu Choi, Jason Cong, Jie Wang

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

SODA: stencil with optimized dataflow architecture.

Yuze Chi, Jason Cong, Peng Wei, Peipei Zhou

Proceedings of the International Conference on Computer-Aided Design, 2018

An Optimal Microarchitecture for Stencil Computation with Data Reuse and Fine-Grained Parallelism: (Abstract Only).

Yuze Chi, Peipei Zhou, Jason Cong

Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017

ForeGraph: Exploring Large-scale Graph Processing on Multi-FPGA Architecture.

Guohao Dai, Tianhao Huang, Yuze Chi, Ningyi Xu, Yu Wang, Huazhong Yang

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016

NXgraph: An efficient graph processing system on a single machine.

Yuze Chi, Guohao Dai, Yu Wang, Guangyu Sun, Guoliang Li, Huazhong Yang

Proceedings of the 32nd IEEE International Conference on Data Engineering, 2016

FPGP: Graph Processing Framework on FPGA A Case Study of Breadth-First Search.

Guohao Dai, Yuze Chi, Yu Wang, Huazhong Yang

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016