Yuyun Liao

According to our database1, Yuyun Liao authored at least 8 papers between 1996 and 2019.

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Bibliography

2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

2018
Loihi: A Neuromorphic Manycore Processor with On-Chip Learning.
IEEE Micro, 2018

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2002
A high-performance and low-power 32-bit multiply-accumulate unit with single-instruction-multiple-data (SIMD) feature.
IEEE J. Solid State Circuits, 2002

2001
An embedded 32-b microprocessor core for low-power and high-performance applications.
IEEE J. Solid State Circuits, 2001

1996
Optimal voltage testing for physically-based faults.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

The Palindrome network for fault-tolerant interconnection.
Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996


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