Yuya Kora

According to our database, Yuya Kora authored at least 4 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2014

MLP-Aware Dynamic Instruction Window Resizing in Superscalar Processors for Adaptively Exploiting Available Parallelism.

Yuya Kora, Kyohei Yamaguchi, Hideki Ando

IEICE Trans. Inf. Syst., 2014

2013

MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP.

Yuya Kora, Kyohei Yamaguchi, Hideki Ando

Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture, 2013

2012

Delay Evaluation of Issue Queue in Superscalar Processors with Banking Tag RAM and Correct Critical Path Identification.

Kyohei Yamaguchi, Yuya Kora, Hideki Ando

IEICE Trans. Inf. Syst., 2012

2011

Evaluation of issue queue delay: Banking tag RAM and identifying correct critical path.

Kyohei Yamaguchi, Yuya Kora, Hideki Ando

Proceedings of the IEEE 29th International Conference on Computer Design, 2011