Yuvraj Singh Dhillon

According to our database, Yuvraj Singh Dhillon authored at least 12 papers between 2003 and 2007.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2007

Delay-Assignment-Variation Based Optimization of Digital CMOS Circuits for Low Power Consumption.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee

J. Low Power Electron., 2007

2006

Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh

IEEE Trans. Very Large Scale Integr. Syst., 2006

2005

Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages.

Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh

IEEE Trans. Very Large Scale Integr. Syst., 2005

Pseudo Dual Supply Voltage Domino Logic Design.

Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh

J. Low Power Electron., 2005

Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance.

Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh

Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Cecilia Metra

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee

Proceedings of the 2005 Design, 2005

Low-power domino circuits using NMOS pull-up on off-critical paths.

Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Low-power dual V_th pseudo dual V_dd domino circuits.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh

Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004

Sizing CMOS Circuits for Increased Transient Error Tolerance.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

2003

An O(N)Supply Voltage Assignment Algorithm for Low-Energy Serially Connected CMOS Modules and a Heuristic Extension to Acyclic Data Flow Graphs.

Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Kyu-won Choi, Abhijit Chatterjee

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Algorithm for Achieving Minimum Energy Consumption in CMOS Circuits Using Multiple Supply and Threshold Voltages at the Module Level.

Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Hsien-Hsin S. Lee

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003