Yuuri Sugihara

According to our database, Yuuri Sugihara authored at least 6 papers between 2006 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

Performance optimization by track swapping on critical paths utilizing random variations for FPGAS.

Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the FPL 2008, 2008

A variation-aware constant-order optimization scheme utilizing delay detectors to search for fastest paths on FPGAS.

Kazutoshi Kobayashi, Yohei Kume, Cam Lai Ngo, Yuuri Sugihara, Hidetoshi Onodera

Proceedings of the FPL 2008, 2008

Speed and yield enhancement by track swapping on critical paths utilizing random variations for FPGAs.

Yuuri Sugihara, Yohei Kume, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, 2008

2007

A 90 nm 48 x 48 LUT-Based FPGA Enhancing Speed and Yield Utilizing Within-Die Delay Variations.

Kazutoshi Kobayashi, Kazuya Katsuki, Manabu Kotani, Yuuri Sugihara, Yohei Kume, Hidetoshi Onodera

IEICE Trans. Electron., 2007

A 90nm 8×16 FPGA Enhancing Speed and Yield Utilizing Within-Die Variations.

Yuuri Sugihara, Manabu Kotani, Kazuya Katsuki, Kazutoshi Kobayashi, Hidetoshi Onodera

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.

Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006