Yuuki Araga

According to our database, Yuuki Araga authored at least 14 papers between 2010 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2021

Analysis and evaluation of noise coupling between through-silicon-vias.

Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

IEICE Electron. Express, 2021

Landside capacitor efficacy among multi-chip-module using Si-interposer.

Yuuki Araga, Ryo Kasai, Daisuke Tanaka, Yoshihide Murakami, Kyoshi Mihara, Kazuo Makida, Hiroki Sonoda, Makoto Nagata, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

IEICE Electron. Express, 2021

2020

Si-Backside Protection Circuits Against Physical Security Attacks on Flip-Chip Devices.

Takuji Miki, Makoto Nagata, Hiroki Sonoda, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

IEEE J. Solid State Circuits, 2020

2019

Over-the-top Si Interposer Embedding Backside Buried Metal PDN to Reduce Power Supply Impedance of Large Scale Digital ICs.

Takuji Miki, Makoto Nagata, Akihiro Tsukioka, Noriyuki Miura, Takaaki Okidono, Yuuki Araga, Naoya Watanabe, Haruo Shimamoto, Katsuya Kikuchi

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

Electrostatic Shield TSVs to Suppress Coupling Among Stacked ICs.

Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi

Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019

2018

A study on substrate noise coupling among TSVs in 3D chip stack.

Yuuki Araga, Makoto Nagata, Joeri De Vos, Geert Van der Plas, Eric Beyne

IEICE Electron. Express, 2018

2015

Guard-ring monitoring system for inspecting defects in TSV-based data buses.

Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi

Proceedings of the 2015 International 3D Systems Integration Conference, 2015

2014

Substrate monitoring system for inspecting defects in TSV-based data buses.

Yuuki Araga, Kikuchi Katsuya, Masahiro Aoyagi

Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013

Performance Evaluation of Probing Front-End Circuits for On-Chip Noise Monitoring.

Yuuki Araga, Nao Ueda, Yasumasa Takagi, Makoto Nagata

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Noise analysis using on-chip waveform monitor in bandgap voltage references.

Akitaka Murata, Shuji Agatsuma, Daisaku Ikoma, Kouji Ichikawa, Takahiro Tsuda, Makoto Nagata, Kumpei Yoshikawa, Yuuki Araga, Yuji Harada

Proceedings of the 9th International Workshop on Electromagnetic Compatibility of Integrated Circuits, 2013

2011

A Diagnosis Testbench of Analog IP Cores for Characterization of Substrate Coupling Strength.

Takushi Hashida, Yuuki Araga, Makoto Nagata

IEICE Trans. Electron., 2011

A diagnosis testbench of analog IP cores against on-chip environmental disturbances.

Takushi Hashida, Yuuki Araga, Makoto Nagata

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

In-tier diagnosis of power domains in 3D TSV ICs.

Yuuki Araga, Makoto Nagata, Geert Van der Plas, Jaemin Kim, Nikolaos Minas, Pol Marchal, Youssef Travaly, Michael Libois, Antonio La Manna, Wenqi Zhang, Eric Beyne

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010

An on-chip waveform capturing technique pursuing minimum cost of integration.

Yuuki Araga, Takushi Hashida, Makoto Nagata

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010