Yuteng Zhou

Orcid: 0000-0002-3551-1295

According to our database1, Yuteng Zhou authored at least 8 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2019
RoadNet: An 80-mW Hardware Accelerator for Road Detection.
IEEE Embed. Syst. Lett., 2019

A 20 TOp/s/W Binary Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
VLSI design of a power-efficient object detector using PCANet.
IEICE Electron. Express, 2018

2017
Deep learning binary neural network on an FPGA.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

An FPGA prototype of dual link algorithm for MIMO interference network.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

2016
A system-on-chip FPGA design for real-time traffic signal recognition system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
A pipeline architecture for traffic sign classification on an FPGA.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

FPGA Design for PCANet Deep Learning Network.
Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015


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