Yutaka Y. Nakamura
According to our database1,
Yutaka Y. Nakamura
authored at least 4 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
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2022
2024
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2024
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
Proceedings of the 35th IEEE Hot Chips Symposium, 2023
2015
TrueNorth: Design and Tool Flow of a 65 mW 1 Million Neuron Programmable Neurosynaptic Chip.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015
2014
Real-Time Scalable Cortical Computing at 46 Giga-Synaptic OPS/Watt with ~100× Speedup in Time-to-Solution and ~100, 000× Reduction in Energy-to-Solution.
Proceedings of the International Conference for High Performance Computing, 2014