Yutaka Tashiro

According to our database1, Yutaka Tashiro authored at least 13 papers between 1991 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

On csauthors.net:

Bibliography

2007
Single-Chip MPEG-2 422P@HL CODEC LSI With Multichip Configuration for Large Scale Processing Beyond HDTV Level.
IEEE Trans. Very Large Scale Integr. Syst., 2007

2006
NTT's technologies for next-generation video services.
Comput. Entertain., 2006

2003
Single-Chip MPEG-2 422P@HL CODEC LSI with Multi-Chip Configuration for Large Scale Processing beyond HDTV Level.
Proceedings of the 2003 Design, 2003

A 1.1 W single-chip MPEG-2 HDTV codec LSI for embedding in consumer-oriented mobile codec systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

1999
Concurrent and collaborative methodologies in short TAT LSI design and manufacturing.
Syst. Comput. Jpn., 1999

SuperENC: MPEG-2 video encoder chip.
IEEE Micro, 1999

1996
Two-chip MPEG-2 video encoder.
IEEE Micro, 1996

A real-time motion estimation and compensation LSI with wide search range for MPEG2 video encoding.
IEEE J. Solid State Circuits, 1996

A Hardware/Software Concurrent Design for a Real-Time SP@ML MPEG2 Video-Encoder Chip Set.
Proceedings of the 1996 European Design and Test Conference, 1996

1992
Architecture and implementation of a highly parallel single-chip video DSP.
IEEE Trans. Circuits Syst. Video Technol., 1992

1991
A 300-MPOS video signal processor with a parallel architecture.
IEEE J. Solid State Circuits, December, 1991

An Organized Firmware Verification Environment for the Programmable Image DSP.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

A highly-parallel single-chip DSP architecture for video signal processing.
Proceedings of the 1991 International Conference on Acoustics, 1991


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