Yutaka Mori

According to our database, Yutaka Mori authored at least 8 papers between 1995 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

Feasibility Demonstration of Integrated Fractioanal Joint Switching WSS Applicable for Few-Mode Multicore Fiber.

Yutaka Mori, Kosuke Yamashita, Masahiko Jinno

Proceedings of the Photonics in Switching and Computing, 2018

2017

Unified Architecture of an Integrated SDM-WSS Employing a PLC-Based Spatial Beam Transformer Array for Various Types of SDM Fibers.

Masahiko Jinno, Yutaka Mori

JOCN, 2017

2016

Effects of Adding/Dropping Nyquist WDM Superchannels on Linear and Nonlinear Transmission Impairments in an Elastic Optical Network.

Masahiko Jinno, Takuya Nakagawa, Yutaka Mori, Koichi Maru, Haruna Matsushita

IEICE Trans. Commun., 2016

Unified architecture and design methodology for integrated SDM-WSS employing PLC-based spatial beam transformer array for various types of SDM fibers.

Masahiko Jinno, Yutaka Mori

Proceedings of the Optical Fiber Communications Conference and Exhibition, 2016

2015

Linear and nonlinear impairments when adding and dropping superchannels in an elastic optical network.

Takuya Nakagawa, Yutaka Mori, Koichi Maru, Haruna Matsushita, Masahiko Jinno

Proceedings of the 21st Asia-Pacific Conference on Communications, 2015

2006

High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar.

Jun Yamada, Hiroyuki Adachi, Yutaka Mori, Akihiko Harada, Seishi Okada, Hisashige Ando

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Diagonal routing in high performance microprocessor design.

Noriyuki Ito, Hideaki Katagiri, Ryoichi Yamashita, Hiroshi Ikeda, Hiroyuki Sugiyama, Hiroaki Komatsu, Yoshiyasu Tanamura, Akihiro Yoshitake, Kazuhiro Nonomura, Kinya Ishizaka, Hiroaki Adachi, Yutaka Mori, Yutaka Isoda, Yaroku Sugiyama

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

1995

Register-Transfer Module Selection for Sub-Micron ASIC Design.

Vasily G. Moshnyaga, Yutaka Mori, Keikichi Tamaru

IEICE Trans. Inf. Syst., 1995