Yutaka Masuda
Orcid: 0000-0001-5177-5322
According to our database1,
Yutaka Masuda
authored at least 29 papers
between 2015 and 2024.
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Bibliography
2024
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., January, 2024
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024
2023
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design.
Proceedings of the 36th IEEE International System-on-Chip Conference, 2023
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022
Proceedings of the 28th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2022
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers.
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
2019
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator.
Proceedings of the 2019 IEEE/ACM Workshop on Photonics-Optics Technology Oriented Networking, 2019
2018
IEEE Trans. Very Large Scale Integr. Syst., 2018
Comparing voltage adaptation performance between replica and in-situ timing monitors.
Proceedings of the International Conference on Computer-Aided Design, 2018
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
2016
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
Proceedings of the 2015 IEEE International Test Conference, 2015
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015