Yutaka Arita

According to our database1, Yutaka Arita authored at least 2 papers between 1998 and 1999.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

1999
A 500-MHz pipelined burst SRAM with improved SER immunity.
IEEE J. Solid State Circuits, 1999

1998
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell.
IEEE J. Solid State Circuits, 1998


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