Yuta Yamato

According to our database, Yuta Yamato authored at least 29 papers between 2006 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Reliability-Enhanced ECC-Based Memory Architecture Using In-Field Self-Repair.

Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue

IEICE Trans. Inf. Syst., 2016

Reliability enhancement of embedded memory with combination of aging-aware adaptive in-field self-repair and ECC.

Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Yasuo Sato, Michiko Inoue

Proceedings of the 21th IEEE European Test Symposium, 2016

Timing-Accurate Estimation of IR-Drop Impact on Logic- and Clock-Paths During At-Speed Scan Test.

Stefan Holst, Eric Schneider, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Hans-Joachim Wunderlich, Michael A. Kochte

Proceedings of the 25th IEEE Asian Test Symposium, 2016

2015

An ECC-based memory architecture with online self-repair capabilities for reliability enhancement.

Gian Mayuga, Yuta Yamato, Tomokazu Yoneda, Michiko Inoue, Yasuo Sato

Proceedings of the 20th IEEE European Test Symposium, 2015

2014

Memory block based scan-BIST architecture for application-dependent FPGA testing.

Keita Ito, Tomokazu Yoneda, Yuta Yamato, Kazumi Hatayama, Michiko Inoue

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Parallel Path Delay Fault Simulation for Multi/Many-Core Processors with SIMD Units.

Yussuf Ali, Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue

Proceedings of the 23rd IEEE Asian Test Symposium, 2014

2013

A Capture-Safety Checking Metric Based on Transition-Time-Relation for At-Speed Scan Testing.

Kohei Miyase, Ryota Sakai, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

IEICE Trans. Inf. Syst., 2013

LCTI-SS: Low-Clock-Tree-Impact Scan Segmentation for Avoiding Shift Timing Failures in Scan Testing.

Yuta Yamato, Kohei Miyase, Seiji Kajihara, Xiaoqing Wen, Laung-Terng Wang, Michael A. Kochte

IEEE Des. Test, 2013

2012

A novel capture-safety checking method for multi-clock designs and accuracy evaluation with delay capture circuits.

Kohei Miyase, Masao Aso, Ryou Ootsuka, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Kazunari Enokimoto, Seiji Kajihara

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

A fast and accurate per-cell dynamic IR-drop estimation method for at-speed scan test pattern validation.

Yuta Yamato, Tomokazu Yoneda, Kazumi Hatayama, Michiko Inoue

Proceedings of the 2012 IEEE International Test Conference, 2012

2011

A GA-Based <i>X</i>-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing.

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

IEICE Trans. Inf. Syst., 2011

Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing.

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

IEICE Trans. Inf. Syst., 2011

Power-aware test generation with guaranteed launch safety for at-speed scan testing.

Xiaoqing Wen, Kazunari Enokimoto, Kohei Miyase, Yuta Yamato, Michael A. Kochte, Seiji Kajihara, Patrick Girard, Mohammad Tehranipoor

Proceedings of the 29th IEEE VLSI Test Symposium, 2011

A novel scan segmentation design method for avoiding shift timing failure in scan testing.

Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang

Proceedings of the 2011 IEEE International Test Conference, 2011

SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures.

Michael A. Kochte, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Kazunari Enokimoto, Hans-Joachim Wunderlich

Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Transition-Time-Relation based capture-safety checking for at-speed scan test generation.

Kohei Miyase, Xiaoqing Wen, Masao Aso, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara

Proceedings of the Design, Automation and Test in Europe, 2011

Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling.

Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

A Study of Capture-Safe Test Generation Flow for At-Speed Testing.

Kohei Miyase, Xiaoqing Wen, Seiji Kajihara, Yuta Yamato, Atsushi Takashima, Hiroshi Furukawa, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

High Launch Switching Activity Reduction in At-Speed Scan Testing Using CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme.

Kohei Miyase, Xiaoqing Wen, Hiroshi Furukawa, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

IEICE Trans. Inf. Syst., 2010

2009

A GA-Based Method for High-Quality X-Filling to Reduce Launch Switching Activity in At-speed Scan Testing.

Yuta Yamato, Xiaoqing Wen, Kohei Miyase, Hiroshi Furukawa, Seiji Kajihara

Proceedings of the 2009 15th IEEE Pacific Rim International Symposium on Dependable Computing, 2009

A novel post-ATPG IR-drop reduction scheme for at-speed scan testing in broadcast-scan-based test compression environment.

Kohei Miyase, Yuta Yamato, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

CAT: A Critical-Area-Targeted Test Set Modification Scheme for Reducing Launch Switching Activity in At-Speed Scan Testing.

Kazunari Enokimoto, Xiaoqing Wen, Yuta Yamato, Kohei Miyase, H. Sone, Seiji Kajihara, Masao Aso, Hiroshi Furukawa

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

A Novel Per-Test Fault Diagnosis Method Based on the Extended <i>X</i>-Fault Model for Deep-Submicron LSI Circuits.

Yuta Yamato, Yusuke Nakamura, Kohei Miyase, Xiaoqing Wen, Seiji Kajihara

IEICE Trans. Inf. Syst., 2008

Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-Identification.

Kohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A Capture-Safe Test Generation Scheme for At-Speed Scan Testing.

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Hiroshi Furukawa, Yuta Yamato, Atsushi Takashima, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Kewal K. Saluja

Proceedings of the 13th European Test Symposium, 2008

CTX: A Clock-Gating-Based Test Relaxation and X-Filling Scheme for Reducing Yield Loss Risk in At-Speed Scan Testing.

Hiroshi Furukawa, Xiaoqing Wen, Kohei Miyase, Yuta Yamato, Seiji Kajihara, Patrick Girard, Laung-Terng Wang, Mohammad Tehranipoor

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

A novel scheme to reduce power supply noise for high-quality at-speed scan testing.

Xiaoqing Wen, Kohei Miyase, Seiji Kajihara, Tatsuya Suzuki, Yuta Yamato, Patrick Girard, Yuji Ohsumi, Laung-Terng Wang

Proceedings of the 2007 IEEE International Test Conference, 2007

2006

A Per-Test Fault Diagnosis Method Based on the <i>X</i>-Fault Model.

Xiaoqing Wen, Seiji Kajihara, Kohei Miyase, Yuta Yamato, Kewal K. Saluja, Laung-Terng Wang, Kozo Kinoshita

IEICE Trans. Inf. Syst., 2006

Highly-Guided X-Filling Method for Effective Low-Capture-Power Scan Test Generation.

Xiaoqing Wen, Kohei Miyase, Tatsuya Suzuki, Yuta Yamato, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006