Yusung Kim

According to our database, Yusung Kim authored at least 11 papers between 2012 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

15.2 A 2048x60m4 SRAM Design in Intel 4 with an Around-the-Array Power-Delivery Scheme Using PowerVia.

Daeyeon Kim, Yusung Kim, Ayush Shrivastava, Gyusung Park, Anandkumar Mahadevan Pillai, Kunal Bannore, Tri Doan, Muktadir Rahman, Gwanghyeon Baek, Clifford Ong, Xiaofei Wang, Zheng Guo, Eric Karl

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology.

Yusung Kim, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl

IEEE J. Solid State Circuits, 2023

2020

A 10nm SRAM Design using Gate-Modulated Self-Collapse Write Assist Enabling 175mV VMIN Reduction with Negligible Power Overhead.

Zheng Guo, Jami Wiedemer, Yusung Kim, Prithvee Sundararajan Ramamoorthy, Prateeksha Bindiganavile Sathyaprasad, Smita Shridharan, Daeyeon Kim, Eric Karl

Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2016

Spin-Transfer Torque Devices for Logic and Memory: Prospects and Perspectives.

Xuanyao Fong, Yusung Kim, Karthik Yogendra, Deliang Fan, Abhronil Sengupta, Anand Raghunathan, Kaushik Roy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Spin-Transfer Torque Memories: Devices, Circuits, and Systems.

Xuanyao Fong, Yusung Kim, Rangharajan Venkatesan, Sri Harsha Choday, Anand Raghunathan, Kaushik Roy

Proc. IEEE, 2016

2015

Exploring Spin Transfer Torque Devices for Unconventional Computing.

Kaushik Roy, Deliang Fan, Xuanyao Fong, Yusung Kim, Mrigank Sharad, Somnath Paul, Subho Chatterjee, Swarup Bhunia, Saibal Mukhopadhyay

IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Magnetic Tunnel Junction Mimics Stochastic Cortical Spiking Neurons.

Abhronil Sengupta, Priyadarshini Panda, Parami Wijesinghe, Yusung Kim, Kaushik Roy

CoRR, 2015

2014

AWARE (Asymmetric Write Architecture With REdundant Blocks): A High Write Speed STT-MRAM Cache Architecture.

Kon-Woo Kwon, Sri Harsha Choday, Yusung Kim, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2014

Failure Mitigation Techniques for 1T-1MTJ Spin-Transfer Torque MRAM Bit-cells.

Xuanyao Fong, Yusung Kim, Sri Harsha Choday, Kaushik Roy

IEEE Trans. Very Large Scale Integr. Syst., 2014

Spin Orbit Torque Based Electronic Neuron.

Abhronil Sengupta, Sri Harsha Choday, Yusung Kim, Kaushik Roy

CoRR, 2014

2012

Write-optimized reliable design of STT MRAM.

Yusung Kim, Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos, Kaushik Roy

Proceedings of the International Symposium on Low Power Electronics and Design, 2012