Yushen Fu
Orcid: 0000-0001-6916-0115
According to our database1,
Yushen Fu
authored at least 8 papers
between 2019 and 2024.
Collaborative distances:
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Bibliography
2024
Int. Trans. Oper. Res., November, 2024
2023
A 16-Bit 4.0-GS/s Calibration-Free 65 nm DAC Achieving >70 dBc SFDR and < -80 dBc IM3 Up to 1 GHz With Enhanced Constant-Switching-Activity Data-Weighted-Averaging.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023
FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
A 6.0-GS/s Time-Interleaved DAC Using an Asymmetric Current-Tree Summation Network and Differential Clock Timing Calibration.
IEEE Trans. Very Large Scale Integr. Syst., February, 2023
2022
FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications.
CoRR, 2022
2021
Dynamic Switching Sequence to Compensate the Integral Nonlinearity in Current-Steering DACs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 16-Bit 4.0-GS/s Calibration-Free 65nm DAC with >70dBc SFDR and <-80dBc IM3 up to 1GHz Using Constant-Activity Element Switching.
Proceedings of the 47th ESSCIRC 2021, 2021
2019
Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019