Yury Shikunov

According to our database, Yury Shikunov authored at least 5 papers between 2016 and 2021.

Collaborative distances:

• Dijkstra number of eight.
• Erdős number of eight.

2021

Design Validation of Recurrent Signal Processor FPGA prototype.

Yury Stepchenkov, Dmitry Khilko, Yury Shikunov, Georgy Orlov

Proceedings of the IEEE East-West Design & Test Symposium, 2021

Self-Timed Storage Register Soft Error Tolerance Improvement.

Yury Stepchenkov, Yury Diachenko, Yury Rogdestvenski, Yury Shikunov, Denis Diachenko

Proceedings of the IEEE East-West Design & Test Symposium, 2021

2019

Advanced Indication of the Self-Timed Circuits.

Yuri Stepchenkov, Yuri Diachenko, Yuri Rogdestvenski, Yury Shikunov, Denis Diachenko

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Modeling and debugging tools development for recurrent architecture.

Dmitry Khilko, Yury Stepchenkov, Yury Shikunov, George Orlov

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

2016

Testing of software and hardware simulations of dataflow recurrent digital signal processor.

Yuri Stepchenkov, Dmitry Khilko, Yuri Diachenko, Yury Shikunov, Dimitry Shikunov

Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016