Yuran Qiao

Orcid: 0000-0002-5488-3545

According to our database1, Yuran Qiao authored at least 9 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
Heterogeneous Systolic Array Architecture for Compact CNNs Hardware Accelerators.
IEEE Trans. Parallel Distributed Syst., 2022

2018
MALMM: A multi-array architecture for large-scale matrix multiplication on FPGA.
IEICE Electron. Express, 2018

Towards a Multi-array Architecture for Accelerating Large-scale Matrix Multiplication on FPGAs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Towards a Uniform Template-based Architecture for Accelerating 2D and 3D CNNs on FPGA.
Proceedings of the 2018 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2018

2017
FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency.
Concurr. Comput. Pract. Exp., 2017

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA.
Proceedings of the Network and Parallel Computing, 2017

2015
Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2015

2014
Automated Transformation of GPU-Specific OpenCL Kernels Targeting Performance Portability on Multi-Core/Many-Core CPUs.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

2013
ACF: Networks-on-Chip Deadlock Recovery with Accurate Detection and Elastic Credit.
Proceedings of the Advanced Parallel Processing Technologies, 2013


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