Yunteng Huang

According to our database, Yunteng Huang authored at least 5 papers between 1998 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2006

A 2.5-Gb/s Multi-Rate 0.25-$\mu$m CMOS Clock and Data Recovery Circuit Utilizing a Hybrid Analog/Digital Loop Filter and All-Digital Referenceless Frequency Acquisition.

Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Douglas Pastorello, Eric T. King, Qicheng Yu, Dan B. Kasha, Philip Steiner, Ligang Zhang, Jerrell P. Hein, Bruce Del Signore

IEEE J. Solid State Circuits, 2006

A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation.

Derrick C. Wei, Yunteng Huang, Bruno W. Garlepp, Jerrell P. Hein

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter.

Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

1999

MOSFET-only switched-capacitor circuits in digital CMOS technology.

Hirokazu Yoshizawa, Yunteng Huang, Paul F. Ferguson Jr., Gabor C. Temes

IEEE J. Solid State Circuits, 1999

1998

Offset- and gain-compensated track-and-hold stages.

Yunteng Huang, Gabor C. Temes, Paul F. Ferguson Jr.

Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998