Yunsup Lee

According to our database1, Yunsup Lee authored at least 27 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2020
Managing Chip Design Complexity in the Domain-Specific SoC Era.
Proceedings of the IEEE Symposium on VLSI Circuits, 2020

2017
A RISC-V Processor SoC With Integrated Power Management at Submicrosecond Timescales in 28 nm FD-SOI.
IEEE J. Solid State Circuits, 2017


2016
Decoupled Vector-Fetch Architecture with a Scalarizing Compiler.
PhD thesis, 2016

An Agile Approach to Building RISC-V Microprocessors.
IEEE Micro, 2016

A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI.
IEEE J. Solid State Circuits, 2016

Strober: Fast and Accurate Sample-Based Energy Simulation for Arbitrary RTL.
Proceedings of the 43rd ACM/IEEE Annual International Symposium on Computer Architecture, 2016

Sub-microsecond adaptive voltage scaling in a 28nm FD-SOI processor SoC.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
Single-chip microprocessor that communicates directly using light.
Nat., 2015

A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI.
Proceedings of the Symposium on VLSI Circuits, 2015

Flexible software profiling of GPU architectures.
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015

Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking.
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015

2014
Exploring the Design Space of SPMD Divergence Management on Data-Parallel Architectures.
Proceedings of the 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014

A 45nm 1.3GHz 16.7 double-precision GFLOPS/W RISC-V processor with vector accelerators.
Proceedings of the ESSCIRC 2014, 2014

2013
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators.
ACM Trans. Comput. Syst., 2013

GPU Scripting and Code Generation with PyCUDA
CoRR, 2013

Hardware/software codesign for mobile speech recognition.
Proceedings of the 14th Annual Conference of the International Speech Communication Association, 2013

The RISC-V instruction set.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Measuring the gap between programmable and fixed-function accelerators: A case study on speech recognition.
Proceedings of the 2013 IEEE Hot Chips 25 Symposium (HCS), 2013

Convergence and scalarization for data-parallel architectures.
Proceedings of the 2013 IEEE/ACM International Symposium on Code Generation and Optimization, 2013

2012
SRAM Assist Techniques for Operation in a Wide Voltage Range in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2012

PyCUDA and PyOpenCL: A scripting-based approach to GPU run-time code generation.
Parallel Comput., 2012

Chisel: constructing hardware in a Scala embedded language.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
The Maven vector-thread architecture.
Proceedings of the 2011 IEEE Hot Chips 23 Symposium (HCS), 2011

2010
RAMP gold: an FPGA-based architecture simulator for multiprocessors.
Proceedings of the 47th Design Automation Conference, 2010

2009
PyCUDA: GPU Run-Time Code Generation for High-Performance Computing
CoRR, 2009

Efficient, high-quality image contour detection.
Proceedings of the IEEE 12th International Conference on Computer Vision, ICCV 2009, Kyoto, Japan, September 27, 2009


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