Yunseong Jo

According to our database, Yunseong Jo authored at least 7 papers between 2022 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 500-MS/s 8-bit SAR ADC Generated from an Automated Layout Generation Framework in 14-nm FinFET Technology.

Yunseong Jo, Taeseung Kang, Jeonghyu Yang, Jaeduk Han

Proceedings of the 30th Asia and South Pacific Design Automation Conference, 2025

2024

A 32-Gb/s Single-Ended PAM-4 Transceiver With Asymmetric Termination and Equalization Techniques for Next-Generation Memory Interfaces.

Hyuntae Kim, Yunseong Jo, Sanghun Lee, Eunsang Lee, Young Choi, Jaewoo Park, Myoungbo Kwak, Jung-Hwan Choi, Youngdon Choi, Jaeduk Han

IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024

Analysis of Test Environment Configuration for High-Speed Link Chip Measurement.

Yunseong Jo, Hyuntae Kim, Jaeduk Han

Proceedings of the 21st International SoC Design Conference, 2024

2023

LAYGO2: A Custom Layout Generation Engine Based on Dynamic Templates and Grids for Advanced CMOS Technologies.

Taeho Shin, Dongjun Lee, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2023

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS.

Hyuntae Kim, Hyeongmin Seo, Yunseong Jo, Changsik Yoo, Jaeduk Han

IEEE Trans. Circuits Syst. II Express Briefs, April, 2023

2022

The effect of virtual reality media characteristics on flow and learning transfer in job training: The moderating effect of presence.

Youn Gu Kang, Hae-Deok Song, Hyejoo Yun, Yunseong Jo

J. Comput. Assist. Learn., 2022

A Custom IC Layout Generation Engine Based on Dynamic Templates and Grids.

Taeho Shin, Dongjun Lee, Dongwhee Kim, Gaeryun Sung, Wookjin Shin, Yunseong Jo, Hyungjoo Park, Jaeduk Han

CoRR, 2022