Yunsaing Kim
According to our database1,
Yunsaing Kim
authored at least 11 papers
between 2012 and 2015.
Collaborative distances:
Collaborative distances:
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Bibliography
2015
A 16.8 Gbps/Channel Single-Ended Transceiver in 65 nm CMOS for SiP-Based DRAM Interface on Si-Carrier Channel.
IEEE J. Solid State Circuits, 2015
A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications.
Proceedings of the Symposium on VLSI Circuits, 2015
Crosstalk-included eye-diagram estimation for high-speed silicon, organic, and glass interposer channels on 2.5D/3D IC.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface.
IEEE J. Solid State Circuits, 2014
25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A 16.8Gbps/channel single-ended transceiver in 65nm CMOS for SiP based DRAM interface on Si-carrier channel.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
A 1.0-ns/1.0-V Delay-Locked Loop With Racing Mode and Countered CAS Latency Controller for DRAM Interfaces.
IEEE J. Solid State Circuits, 2012
A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 1.2V 38nm 2.4Gb/s/pin 2Gb DDR4 SDRAM with bank group and ×4 half-page architecture.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012