Yunheung Paek

Orcid: 0000-0002-6412-2926

According to our database1, Yunheung Paek authored at least 149 papers between 1996 and 2024.

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Bibliography

2024
An Efficient Hardware/Software Co-Design for FALCON on Low-End Embedded Systems.
IEEE Access, 2024

Enhancing a Lock-and-Key Scheme With MTE to Mitigate Use-After-Frees.
IEEE Access, 2024

MetaSafe: Compiling for Protecting Smart Pointer Metadata to Ensure Safe Rust Integrity.
Proceedings of the 33rd USENIX Security Symposium, 2024

VFLIP: A Backdoor Defense for Vertical Federated Learning via Identification and Purification.
Proceedings of the Computer Security - ESORICS 2024, 2024

2023
Optimizing Hardware Resource Utilization for Accelerating the NTRU-KEM Algorithm.
Comput., December, 2023

Ambassy: A Runtime Framework to Delegate Trusted Applications in an ARM/FPGA Hybrid System.
IEEE Trans. Mob. Comput., 2023

Exploring effective uses of the tagged memory for reducing bounds checking overheads.
J. Supercomput., 2023

ZOMETAG: Zone-Based Memory Tagging for Fast, Deterministic Detection of Spatial Memory Violations on ARM.
IEEE Trans. Inf. Forensics Secur., 2023

Modeling and Library Support for Early-Stage Exploration of Sparse Tensor Accelerator Designs.
IEEE Access, 2023

TRust: A Compilation Framework for In-process Isolation to Protect Safe Rust against Untrusted Code.
Proceedings of the 32nd USENIX Security Symposium, 2023

Exploring Clustered Federated Learning's Vulnerability against Property Inference Attack.
Proceedings of the 26th International Symposium on Research in Attacks, 2023

Area-Efficient Accelerator for the Full NTRU-KEM Algorithm.
Proceedings of the Computational Science and Its Applications - ICCSA 2023 Workshops, 2023

FLGuard: Byzantine-Robust Federated Learning via Ensemble of Contrastive Models.
Proceedings of the Computer Security - ESORICS 2023, 2023

KVSEV: A Secure In-Memory Key-Value Store with Secure Encrypted Virtualization.
Proceedings of the 2023 ACM Symposium on Cloud Computing, SoCC 2023, 2023

Sfitag: Efficient Software Fault Isolation with Memory Tagging for ARM Kernel Extensions.
Proceedings of the 2023 ACM Asia Conference on Computer and Communications Security, 2023

2022
Data Embedding Scheme for Efficient Program Behavior Modeling With Neural Networks.
IEEE Trans. Emerg. Top. Comput. Intell., 2022

Accelerating N-Bit Operations over TFHE on Commodity CPU-FPGA.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Precise Extraction of Deep Learning Models via Side-Channel Attacks on Edge/Endpoint Devices.
Proceedings of the Computer Security - ESORICS 2022, 2022

XTENSTORE: Fast Shielded In-memory Key-Value Store on a Hybrid x86-FPGA System.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Practical Binary Code Similarity Detection with BERT-based Transferable Similarity Learning.
Proceedings of the Annual Computer Security Applications Conference, 2022

2021
A metadata-driven approach to efficiently detect code-reuse attacks on ARM multiprocessors.
J. Supercomput., 2021

Learn2Evade: Learning-Based Generative Model for Evading PDF Malware Classifiers.
IEEE Trans. Artif. Intell., 2021

MeetGo: A Trusted Execution Environment for Remote Applications on FPGA.
IEEE Access, 2021

Panop: Mimicry-Resistant ANN-Based Distributed NIDS for IoT Networks.
IEEE Access, 2021

2020
PrOS: Light-Weight Privatized Se cure OSes in ARM TrustZone.
IEEE Trans. Mob. Comput., 2020

SBGen: A Framework to Efficiently Supply Runtime Information for a Learning-Based HIDS for Multiple Virtual Machines.
IEEE Access, 2020

Hawkware: Network Intrusion Detection based on Behavior Analysis with ANNs on an IoT Device.
Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

TRUSTORE: Side-Channel Resistant Storage for SGX using Intel Hybrid CPU-FPGA.
Proceedings of the CCS '20: 2020 ACM SIGSAC Conference on Computer and Communications Security, 2020

2019
DADE: a fast data anomaly detection engine for kernel integrity monitoring.
J. Supercomput., 2019

Safe and Efficient Implementation of a Security System on ARM using Intra-level Privilege Separation.
ACM Trans. Priv. Secur., 2019

KI-Mon ARM: A Hardware-Assisted Event-triggered Monitoring Platform for Mutable Kernel Object.
IEEE Trans. Dependable Secur. Comput., 2019

LizarMong: Excellent Key Encapsulation Mechanism based on RLWE and RLWR.
IACR Cryptol. ePrint Arch., 2019

ActiMon: Unified JOP and ROP Detection With Active Function Lists on an SoC FPGA.
IEEE Access, 2019

uXOM: Efficient eXecute-Only Memory on ARM Cortex-M.
Proceedings of the 28th USENIX Security Symposium, 2019

CRCount: Pointer Invalidation with Reference Counting to Mitigate Use-after-free in Legacy C/C++.
Proceedings of the 26th Annual Network and Distributed System Security Symposium, 2019

Data Randomization for Multi-Variant Execution Environment.
Proceedings of the 2019 International SoC Design Conference, 2019

Real-Time Anomalous Branch Behavior Inference with a GPU-inspired Engine for Machine Learning Models.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

RiskiM: Toward Complete Kernel Protection with Hardware Support.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Developing a custom DSP for vision based human computer interaction applications.
Multim. Tools Appl., 2018

Extended Abstract: Mimicry Resilient Program Behavior Modeling with LSTM based Branch Models.
CoRR, 2018

A dynamic per-context verification of kernel address integrity from external monitors.
Comput. Secur., 2018

Hardware Assisted Randomization of Data.
Proceedings of the Research in Attacks, Intrusions, and Defenses, 2018

Design of a Generic Security Interface for RISC-V Processors and its Applications.
Proceedings of the International SoC Design Conference, 2018

VM-CFI: Control-Flow Integrity for Virtual Machine Kernel Using Intel PT.
Proceedings of the Computational Science and Its Applications - ICCSA 2018, 2018

Hypernel: a hardware-assisted framework for kernel protection without nested paging.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Architectural Supports to Protect OS Kernels from Code-Injection Attacks and Their Applications.
ACM Trans. Design Autom. Electr. Syst., 2017

Using CoreSight PTM to Integrate CRA Monitoring IPs in an ARM-Based SoC.
ACM Trans. Design Autom. Electr. Syst., 2017

Detecting and Preventing Kernel Rootkit Attacks with Bus Snooping.
IEEE Trans. Dependable Secur. Comput., 2017

Optimization techniques to enable execution offloading for 3D video games.
Multim. Tools Appl., 2017

Dynamic Virtual Address Range Adjustment for Intra-Level Privilege Separation on ARM.
Proceedings of the 24th Annual Network and Distributed System Security Symposium, 2017

Instruction-Level Data Isolation for the Kernel on ARM.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Efficient Security Monitoring with the Core Debug Interface in an Embedded Processor.
ACM Trans. Design Autom. Electr. Syst., 2016

Software-Based Selective Validation Techniques for Robust CGRAs Against Soft Errors.
ACM Trans. Embed. Comput. Syst., 2016

Precise execution offloading for applications with dynamic behavior in mobile cloud computing.
Pervasive Mob. Comput., 2016

Energy-Reduction Offloading Technique for Streaming Media Servers.
Mob. Inf. Syst., 2016

LSTM-Based System-Call Language Modeling and Robust Ensemble Method for Designing Host-Based Intrusion Detection Systems.
CoRR, 2016

Hardware-Assisted On-Demand Hypervisor Activation for Efficient Security Critical Code Execution on Mobile Devices.
Proceedings of the 2016 USENIX Annual Technical Conference, 2016

HDFI: Hardware-Assisted Data-Flow Isolation.
Proceedings of the IEEE Symposium on Security and Privacy, 2016

Architectural Supports to Protect OS Kernels from Code-Injection Attacks.
Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, 2016

A hardware-based technique for efficient implicit information flow tracking.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Integration of ROP/JOP monitoring IPs in an ARM-based SoC.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A Survey and Design of a Scalable Mobile Edge Cloud Platform for the Smart IoT Devices and It's Applications.
Proceedings of the Advances in Computer Science and Ubiquitous Computing, 2016

2015
Implementing an Application-Specific Instruction-Set Processor for System-Level Dynamic Program Analysis Engines.
ACM Trans. Design Autom. Electr. Syst., 2015

Mantis: Efficient Predictions of Execution Time, Energy Usage, Memory Usage and Network Usage on Smart Mobile Devices.
IEEE Trans. Mob. Comput., 2015

Towards a practical solution to detect code reuse attacks on ARM mobile devices.
Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Extrax: security extension to extract cache resident information for snoop-based external monitors.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Efficient dynamic information flow tracking on a processor with core debug interface.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Energy Consumption Reduction Technique on Smart Devices for Communication-Intensive Applications.
Proceedings of the Advances in Computer Science and Ubiquitous Computing, 2015

Accelerating bootstrapping in FHEW using GPUs.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Techniques to Minimize State Transfer Costs for Dynamic Execution Offloading in Mobile Cloud Computing.
IEEE Trans. Mob. Comput., 2014

Improving performance of loops on DIAM-based VLIW architectures.
Proceedings of the SIGPLAN/SIGBED Conference on Languages, 2014

CMcloud: Cloud Platform for Cost-Effective Offloading of Mobile Applications.
Proceedings of the 14th IEEE/ACM International Symposium on Cluster, 2014

2013
Architecture customization of on-chip reconfigurable accelerators.
ACM Trans. Design Autom. Electr. Syst., 2013

Reducing instruction bit-width for low-power VLIW architectures.
ACM Trans. Design Autom. Electr. Syst., 2013

Dynamic code duplication with vulnerability awareness for soft error detection on VLIW architectures.
ACM Trans. Archit. Code Optim., 2013

KI-Mon: A Hardware-assisted Event-triggered Monitoring Platform for Mutable Kernel Object.
Proceedings of the 22th USENIX Security Symposium, Washington, DC, USA, August 14-16, 2013, 2013

Mantis: Automatic Performance Prediction for Smartphone Applications.
Proceedings of the 2013 USENIX Annual Technical Conference, 2013

Fast dynamic execution offloading for efficient mobile cloud computing.
Proceedings of the 2013 IEEE International Conference on Pervasive Computing and Communications, 2013

Selective validations for efficient protections on Coarse-Grained Reconfigurable Architectures.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Improving performance of nested loops on reconfigurable array processors.
ACM Trans. Archit. Code Optim., 2012

Compiler and microarchitectural approaches for register file thermal management.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Dynamic Operands Insertion for VLIW Architecture with a Reduced Bit-width Instruction Set.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

An Efficient Management Technique for Fast SRAM Subsystems.
Proceedings of the Convergence and Hybrid Information Technology, 2012

Vigilare: toward snoop-based kernel integrity monitor.
Proceedings of the ACM Conference on Computer and Communications Security, 2012

Exploiting Both Pipelining and Data Parallelism with SIMD Reconfigurable Architecture.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Memory access optimization in compilation for coarse-grained reconfigurable architectures.
ACM Trans. Design Autom. Electr. Syst., 2011

High Throughput Data Mapping for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Fast graph-based instruction selection for multi-output instructions.
Softw. Pract. Exp., 2011

I<sup>2</sup>CRF: Incremental interconnect customization for embedded reconfigurable fabrics.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
Two versions of architectures for dynamic implied addressing mode.
J. Syst. Archit., 2010

Operation and data mapping for CGRAs with multi-bank memory.
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, 2010

Memory-Aware Application Mapping on Coarse-Grained Reconfigurable Arrays.
Proceedings of the High Performance Embedded Architectures and Compilers, 2010

Implementing dynamic implied addressing mode for multi-output instructions.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2009

Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.
Trans. High Perform. Embed. Archit. Compil., 2009

Register coalescing techniques for heterogeneous register architecture with copy sifting.
ACM Trans. Embed. Comput. Syst., 2009

Compiler-in-the-Loop Design Space Exploration Framework for Energy Reduction in Horizontally Partitioned Cache Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Adaptive Scratch Pad Memory Management for Dynamic Behavior of Multimedia Applications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A new addressing mode for the encoding space problem on embedded processors.
Proceedings of the IEEE 7th Symposium on Application Specific Processors, 2009

Management environment of mass Windows Servers for server-based computing.
Proceedings of the 2009 International Conference on Information Networking, 2009

Orthogonal Instruction Encoding for a 16-bit Embedded Processor with Dynamic Implied Addressing Mode.
Proceedings of the 11th IEEE International Conference on High Performance Computing and Communications, 2009

Iterative Algorithm for Compound Instruction Selection with Register Coalescing.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

2008
A retargetable parallel-programming framework for MPSoC.
ACM Trans. Design Autom. Electr. Syst., 2008

Register File Power Reduction Using Bypass Sensitive Compiler.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Compiler driven data layout optimization for regular/irregular array access patterns.
Proceedings of the 2008 ACM SIGPLAN/SIGBED Conference on Languages, 2008

Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors.
Proceedings of the Design, Automation and Test in Europe, 2008

SPKM : A novel graph drawing based algorithm for application mapping onto coarse-grained reconfigurable architectures.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Introduction to the special LCTES'05 issue.
ACM Trans. Embed. Comput. Syst., 2007

Automatic Design Space Exploration of Register Bypasses in Embedded Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Efficient embedded code generation with multiple load/store instructions.
Softw. Pract. Exp., 2007

Optimistic coalescing for heterogeneous register architectures.
Proceedings of the 2007 ACM SIGPLAN/SIGBED Conference on Languages, 2007

A code-generator generator for multi-output instructions.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors.
Proceedings of the Compiler Construction, 16th International Conference, 2007

Software controlled memory layout reorganization for irregular array access patterns.
Proceedings of the 2007 International Conference on Compilers, 2007

2006
VISTA: VPO interactive system for tuning applications.
ACM Trans. Embed. Comput. Syst., 2006

Bypass aware instruction scheduling for register file power reduction.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Power-conscious configuration cache structure and code mapping for coarse-grained reconfigurable architecture.
Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs.
Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2006

Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm.
Proceedings of the Emerging Directions in Embedded and Ubiquitous Computing, 2006

Automatic generation of operation tables for fast exploration of bypasses in embedded processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A spatial mapping algorithm for heterogeneous coarse-grained reconfigurable architectures.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Compiler transformations for effectively exploiting a zero overhead loop buffer.
Softw. Pract. Exp., 2005

2004
Fast memory bank assignment for fixed-point digital signal processors.
ACM Trans. Design Autom. Electr. Syst., 2004

Code optimizations for a VLIW-style network processing unit.
Softw. Pract. Exp., 2004

Exploiting Parallelism in Memory Operations for Code Optimization.
Proceedings of the Languages and Compilers for High Performance Computing, 2004

2003
Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Finding effective optimization phase sequences.
Proceedings of the 2003 Conference on Languages, 2003

A Quantitative Comparison of Two Retargetable Compilation Approaches.
Proceedings of the 32nd International Conference on Parallel Processing (ICPP 2003), 2003

2002
An Advanced Compiler Framework for Non-Cache-Coherent Multiprocessors.
IEEE Trans. Parallel Distributed Syst., 2002

Efficient and precise array access analysis.
ACM Trans. Program. Lang. Syst., 2002

A proof method for the correctness of modularized 0CFA.
Inf. Process. Lett., 2002

Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms.
Proceedings of the 2002 Joint Conference on Languages, 2002

Experience with a retargetable compiler for a commercial network processor.
Proceedings of the International Conference on Compilers, 2002

A Study on Data Allocation of On-Chip Dual Memory Banks.
Proceedings of the 6th Annual Workshop on Interaction between Compilers and Computer Architecture (INTERACT-6 2002), 2002

2001
Unified Interprocedural Parallelism Detection.
Int. J. Parallel Program., 2001

A Parallel Programming Environment for a V-Busbased PC-cluste.
Proceedings of the 2001 IEEE International Conference on Cluster Computing (CLUSTER 2001), 2001

The very portable optimizer for digital signal processors.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
A Comparative Analysis of Dependence Testing Mechanisms.
Proceedings of the Languages and Compilers for Parallel Computing, 2000

1999
The Access Region Test.
Proceedings of the Languages and Compilers for Parallel Computing, 1999

Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

1998
Simplification of Array Access Patterns for Compiler Optimizations.
Proceedings of the ACM SIGPLAN '98 Conference on Programming Language Design and Implementation (PLDI), 1998

Experimental Study of Compiler Techniques for NUMA Machines.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

Parallelization of Benchmarks for Scalable Shared-Memory Multiprocessors.
Proceedings of the 1998 International Conference on Parallel Architectures and Compilation Techniques, 1998

1997
Compiling for Distributed Memory Multiprocessors Based on Access Region Analysis
PhD thesis, 1997

Compiling for Scalable Multiprocessors with Polaris.
Parallel Process. Lett., 1997

Compiler Techniques for Effective Communication on Distributed-Memory Multiprocessors.
Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996
Parallel Programming with Polaris.
Computer, 1996

Automatic Parallelization for Non-cache Coherent Multiprocessors.
Proceedings of the Languages and Compilers for Parallel Computing, 1996

Restructuring Programs for High-Speed Computers with Polaris.
Proceedings of the 1996 International Conference on Parallel Processing Workshop, 1996


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