Yung-Yuan Chen
Orcid: 0000-0002-6156-5473
According to our database1,
Yung-Yuan Chen
authored at least 32 papers
between 1990 and 2024.
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Bibliography
2024
Development of an Effective Corruption-Related Scenario-Based Testing Approach for Robustness Verification and Enhancement of Perception Systems in Autonomous Driving.
Sensors, 2024
2021
SoC-Level Safety-Oriented Design Process in Electronic System Level Development Environment.
J. Circuits Syst. Comput., 2021
Proceedings of the 51st Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2021
2020
Proceedings of the 2020 International Conference on Artificial Intelligence in Information and Communication, 2020
Analysis of the Effect of Automotive Ethernet Camera Image Quality on Object Detection Models.
Proceedings of the 2020 International Conference on Artificial Intelligence in Information and Communication, 2020
2019
ISO 26262 ASIL-Oriented Hardware Design Framework for Safety-Critical Automotive Systems.
Proceedings of the 2019 IEEE International Conference on Connected Vehicles and Expo, 2019
2018
Proceedings of the 48th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2018
2016
Proceedings of the 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2016
2015
An intelligent brake-by-wire system design and analysis in accordance with ISO-26262 functional safety standard.
Proceedings of the International Conference on Connected Vehicles and Expo, 2015
Proceedings of the International Conference on Connected Vehicles and Expo, 2015
2012
Proceedings of the International Conference on Information and Communication Technology Convergence, 2012
Proceedings of the 2012 International Conference on Connected Vehicles and Expo, 2012
2010
Reliable data path design of VLIW processor cores with comprehensive error-coverage assessment.
Microprocess. Microsystems, 2010
2009
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009
2008
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008
Proceedings of the Second International Conference on Secure System Integration and Reliability Improvement, 2008
Proceedings of the 14th IEEE Pacific Rim International Symposium on Dependable Computing, 2008
2006
Proceedings of the Embedded and Ubiquitous Computing, International Conference, 2006
Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006
2005
IEEE Trans. Computers, 2005
2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
1999
Proceedings of the Dependable Computing, 1999
1997
IEEE Trans. Computers, 1997
1995
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
1994
Modeling the Reliability of a Class of Fault-Tolerant VLSI/WSI Systems Based on Multiple-Level Redundancy.
IEEE Trans. Computers, 1994
Proceedings of the Dependable Computing, 1994
1993
Yield Analysis of Reconfigurable Array Processors Based on Multiple-Level Redundancy.
IEEE Trans. Computers, 1993
Reliability, Reconfiguration, and Spare Allocation Issues in Binary-Tree Architectures Based on Multiple-Level Redundancy.
IEEE Trans. Computers, 1993
1990
An analysis of a reconfigurable binary tree architecture based on multiple-level redundancy.
Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990