Yung Sern Tan

According to our database1, Yung Sern Tan authored at least 9 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2016
An inductorless transimpedance amplifier design for 10 Gb/s optical communication using 0.18-µm CMOS.
Proceedings of the International Symposium on Integrated Circuits, 2016

2013
A low power wideband differential transimpedance amplifier for optical receivers in 0.18-μm CMOS.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A current-mode stimulator circuit with two-step charge balancing background calibration.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A Dual-Loop Clock and Data Recovery Circuit With Compact Quarter-Rate CMOS Linear Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A 160 nW 25 kS/s 9-bit SAR ADC for neural signal recording applications.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

A 57∼66GHz CMOS voltage-controlled oscillator using tunable differential inductor.
Proceedings of the International SoC Design Conference, 2012

Low power implantable neural recording front-end.
Proceedings of the International SoC Design Conference, 2012

Integrated circuits design for neural recording sensor interface.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

A 9.87 nW 1 kS/s 8.7 ENOB SAR ADC for implantable epileptic seizure detection microsystems.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012


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