Yung-Hsiang Ho

According to our database, Yung-Hsiang Ho authored at least 7 papers between 2012 and 2016.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2016

A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation.

Yung-Hsiang Ho, Chia-Yu Yao

IEEE Trans. Very Large Scale Integr. Syst., 2016

A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register.

Yung-Hsiang Ho, Chia-Yu Yao

IEEE Trans. Very Large Scale Integr. Syst., 2016

2015

Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.

Chia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang

IEEE Trans. Very Large Scale Integr. Syst., 2015

Simulating delta-sigma analog-to-digital converters with the Op-Amp nonlinearity using the Newton's method.

Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia, Jyun-Jie Huang

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014

Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space.

Chia-Yu Yao, Wei-Chun Hsia, Yung-Hsiang Ho

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013

A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism.

Chia-Yu Yao, Yung-Hsiang Ho

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

Optimization of the hybrid asymmetric-FIR/analog square-root filters.

Chia-Yu Yao, Yung-Hsiang Ho, Wei-Chun Hsia

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012