Yung-Hsiang Ho

According to our database1, Yung-Hsiang Ho authored at least 7 papers between 2012 and 2016.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register.
IEEE Trans. Very Large Scale Integr. Syst., 2016

2015
Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay Line.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Simulating delta-sigma analog-to-digital converters with the Op-Amp nonlinearity using the Newton's method.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
Designing Hardware-Efficient Fixed-Point FIR Filters in an Expanding Subexpression Space.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

2013
A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanism.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012
Optimization of the hybrid asymmetric-FIR/analog square-root filters.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012


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