Yung-Chung Lo

According to our database1, Yung-Chung Lo authored at least 6 papers between 2009 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2015
A 0.6ps jitter 2-16 GHz 130nm CMOS frequency synthesizer for broadband applications.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2013
A Bang-Bang Clock and Data Recovery Using Mixed Mode Adaptive Loop Gain Strategy.
IEEE J. Solid State Circuits, June, 2013

2012
An LC Quadrature VCO Using Capacitive Source Degeneration Coupling to Eliminate Bi-Modal Oscillation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Self-Sustained CMOS Microwave Chemical Sensor Using a Frequency Synthesizer.
IEEE J. Solid State Circuits, 2012

2010
A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback.
IEEE J. Solid State Circuits, 2010

2009
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009


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