Yung-Chuan Su

According to our database, Yung-Chuan Su authored at least 3 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

A Process-Adaptive Cell-Based Cyclic Time-to-Digital Converter Using One-Way Varactor Cells.

Yung-Chuan Su, Shi-Yu Huang

IEEE Trans. Very Large Scale Integr. Syst., March, 2023

Clock-Latency-Aware Fault-Tolerant DLL for Multi-Die Clock Synchronization.

Yung-Chuan Su, Shi-Yu Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

2022

Just-Enough Strategy for Accurate Clock Jitter Measurement Using A Cyclic Time-to-Digital Converter.

Yung-Chuan Su, Shi-Yu Huang

Proceedings of the 19th International SoC Design Conference, 2022