Yung-Ching Hsieh

According to our database, Yung-Ching Hsieh authored at least 6 papers between 1989 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache.

Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu

Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

1993

An efficient layout style for two-metal CMOS leaf cells and its automatic synthesis.

Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1991

LiB: a CMOS cell compiler.

Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

An Efficient Layout Style for 2-Metal CMOS Leaf Cells And Their Automatic Generation.

Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 28th Design Automation Conference, 1991

1990

LiB: A Cell Layout Generator.

Yung-Ching Hsieh, Chi-Yi Hwang, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

An optimal transistor-chaining algorithm for CMOS cell layout.

Chi-Yi Hwang, Yung-Ching Hsieh, Youn-Long Lin, Yu-Chin Hsu

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989