Yung-Chih Liang

According to our database, Yung-Chih Liang authored at least 2 papers in 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2011

A 0.5 V 320 MHz 8 bit×8 bit pipelined multiplier in 130 nm CMOS process.

Wei-Bin Yang, Chao-Cheng Liao, Yung-Chih Liang

Microelectron. J., 2011

Design of power-rail ESD clamp circuit with adjustable holding voltage against mis-trigger or transient-induced latch-on events.

Chih-Ting Yeh, Yung-Chih Liang, Ming-Dou Ker

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011