Yung-Chih Chen

Hao-Ju Chang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

A Flexible Cluster Tool Simulation Framework with Wafer Batch Dispatching Time Recommendation.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Quality Electronic Design, 2023

An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate Identification.

[BibT_eX]

[DOI]

Ting-Yu Yeh

Yueh Cho

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Expanding In-Cone Obfuscated Tree for Anti SAT Attack.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

A Robust Approach to Detecting Non-Equivalent Quantum Circuits Using Specially Designed Stimuli.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Approximate Logic Synthesis by Genetic Algorithm with an Error Rate Guarantee.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Optimization of Reversible Logic Networks with Gate Sharing.

[BibT_eX]

[DOI]

Feng-Jie Chao

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

A High Voltage Driving Chiplet in Standard 0.18-μm CMOS for Micro-Pixelated LED Displays Integrated With LTPS TFTs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2022

LOOPLock 2.0: An Enhanced Cyclic Logic Locking Approach.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

A Don't-Care-Based Approach to Reducing the Multiplicative Complexity in Logic Networks.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Don't Care Computation and De Morgan Transformation for Threshold Logic Network Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Majority Logic Circuit Minimization Using Node Addition and Removal.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

An Approach to Unlocking Cyclic Logic Locking: LOOPLock 2.0.

[BibT_eX]

[DOI]

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

Dynamic Workload Allocation for Edge Computing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Diagnosis for Reconfigurable Single-Electron Transistor Arrays with a More Generalized Defect Model.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2021

An IMU-aided Fitness System.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

Cluster Tool Performance Analysis using Graph Database.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

On Reduction of Computations for Threshold Function Identification.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International System-on-Chip Conference, 2021

On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Towards Deep Learning-Based Sarcopenia Screening with Body Joint Composition Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2021 IEEE International Conference on Image Processing, 2021

1st-Order to 2nd-Order Threshold Logic Gate Transformation with an Enhanced ILP-based Identification Method.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

An Efficient Approximate Node Merging with an Error Rate Guarantee.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

A General Equivalence Checking Framework for Multivalued Logic.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

A New Necessary Condition for Threshold Function Identification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

LOOPLock: Logic Optimization-Based Cyclic Logic Locking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

SMARTLock: SAT Attack and Removal Attack-Resistant Tree-Based Logic Locking.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020

Prediction of chronic kidney disease stages by renal ultrasound imaging.

[BibT_eX]

[DOI]

Enterp. Inf. Syst., 2020

A Dynamic Expansion Order Algorithm for the SAT-based Minimization.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

IMU-based Smart Knee Pad for Walking Distance and Stride Count Measurement.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Rehabilitation System for Limbs using IMUs.

[BibT_eX]

[DOI]

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Accuracy Tolerant Neural Networks Under Aggressive Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A Convolutional Result Sharing Approach for Binarized Neural Network Inference.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Don't-Care-Based Node Minimization for Threshold Logic Networks.

[BibT_eX]

[DOI]

Hao-Ju Chang

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Optimization of Threshold Logic Networks with Node Merging and Wire Replacement.

[BibT_eX]

[DOI]

Fu-Lian Wong

ACM Trans. Design Autom. Electr. Syst., 2019

Threshold Function Identification by Redundancy Removal and Comprehensive Weight Assignments.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Glitch Key-Gate for Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

A Smart Single-Sensor Device for Instantaneously Monitoring Lower Limb Exercises.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

On Synthesizing Memristor-Based Logic Circuits With Minimal Operational Pulses.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Contactless Testing for Prebond Interposers.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Enhancements to SAT Attack: Speedup and Breaking Cyclic Logic Encryption.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2018

Optimization of threshold logic networks with ODC-based node merging.

[BibT_eX]

[DOI]

Fu-Lian Wong

Proceedings of the 2018 International Symposium on VLSI Design, 2018

Using range-equivalent circuits for facilitating bounded sequential equivalence checking.

[BibT_eX]

[DOI]

Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Hybrid Approach to Equivalent Fault Identification for Verification Environment Qualification.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Logic optimization with considering boolean relations.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Efficient synthesis of approximate threshold logic circuits with an error rate guarantee.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

In&Out: Restructuring for threshold logic network optimization.

[BibT_eX]

[DOI]

Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Tree-Based Logic Encryption for Resisting SAT Attack.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

Majority logic circuits optimisation by node merging.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Area-Aware Decomposition for Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

Minimization of Number of Neurons in Voronoi Diagram-Based Artificial Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Multi Scale Comput. Syst., 2016

An Efficient Interpolation-Based Projected Sum of Product Decomposition via Genetic Algorithm.

[BibT_eX]

[DOI]

J. Multiple Valued Log. Soft Comput., 2016

MSPlayer: Multi-Source and Multi-Path Video Streaming.

[BibT_eX]

[DOI]

Ramin Khalili

IEEE J. Sel. Areas Commun., 2016

MajorSat: A SAT solver to majority logic.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

Fast synthesis of threshold logic networks with optimization.

[BibT_eX]

[DOI]

Runyi Wang

Yan-Ping Chang

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Synthesis for Width Minimization in the Single-Electron Transistor Array.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

Correctness Analysis and Power Optimization for Probabilistic Boolean Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Synthesis and verification of cyclic combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Measurement of body joint angles for physical therapy based on mean shift tracking using two low cost Kinect images.

[BibT_eX]

[DOI]

H. J. Lee

K. H. Lin

Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015

Using structural relations for checking combinationality of cyclic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Design, implementation, and evaluation of energy-aware multi-path TCP.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM Conference on Emerging Networking Experiments and Technologies, 2015

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Hybrid LUT and SOP Reconfigurable Architecture.

[BibT_eX]

[DOI]

Po-Yang Hsu

Yi-Yu Liu

J. Inf. Sci. Eng., 2014

Improving Energy Efficiency of MPTCP for Mobile Devices.

[BibT_eX]

[DOI]

CoRR, 2014

SAT-based complete logic implication with application to logic optimization.

[BibT_eX]

[DOI]

Kung-Ming Ji

Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

Multi-source multipath HTTP (mHTTP): a proposal.

[BibT_eX]

[DOI]

Proceedings of the ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2014

How green is multipath TCP for mobile devices?

[BibT_eX]

[DOI]

Proceedings of the 4th workshop on All things cellular: operations, 2014

On bufferbloat and delay analysis of multipath TCP in wireless networks.

[BibT_eX]

[DOI]

Proceedings of the 2014 IFIP Networking Conference, Trondheim, 2014

Cross-layer path management in multi-path transport protocol for mobile devices.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Conference on Computer Communications, 2014

Stage diagnosis for Chronic Kidney Disease based on ultrasonography.

[BibT_eX]

[DOI]

Proceedings of the 11th International Conference on Fuzzy Systems and Knowledge Discovery, 2014

Width minimization in the Single-Electron Transistor array synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Rewiring for threshold logic circuit minimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

MSPlayer: Multi-Source and multi-Path LeverAged YoutubER.

[BibT_eX]

[DOI]

Ramin Khalili

Proceedings of the 10th ACM International on Conference on emerging Networking Experiments and Technologies, 2014

2013

Verification of Reconfigurable Binary Decision Diagram-Based Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

Ching-Yi Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

Multi-Source Multi-Path HTTP (mHTTP): A Proposal.

[BibT_eX]

[DOI]

CoRR, 2013

Pattern generation for Mutation Analysis using Genetic Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A measurement-based study of MultiPath TCP performance over wireless networks.

[BibT_eX]

[DOI]

Proceedings of the 2013 Internet Measurement Conference, 2013

Sensitization criterion for threshold logic circuits and its application.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2013

On reconfigurable single-electron transistor arrays synthesis using reordering techniques.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

2012

Logic Restructuring Using Node Addition and Removal.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A mixed queueing network model of mobility in a campus wireless network.

[BibT_eX]

[DOI]

Jim Kurose

Proceedings of the IEEE INFOCOM 2012, Orlando, FL, USA, March 25-30, 2012, 2012

A probabilistic analysis method for functional qualification under Mutation Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Ultrasonography Image Analysis for Detection and Classification of Chronic Kidney Disease.

[BibT_eX]

[DOI]

Proceedings of the Sixth International Conference on Complex, 2012

2011

A simple queueing network model of mobility in a campus wireless network.

[BibT_eX]

[DOI]

Jim Kurose

Proceedings of the 3rd ACM workshop on Wireless of the students, 2011

A recursive SVD-based self-constructing rule generation for neuro-fuzzy system modeling.

[BibT_eX]

[DOI]

Chen-Sen Ouyang

Chih-Chung Wang

Proceedings of the International Conference on Machine Learning and Cybernetics, 2011

Automated mapping for reconfigurable single-electron transistor arrays.

[BibT_eX]

[DOI]

Proceedings of the 48th Design Automation Conference, 2011

2010

Fast Node Merging With Don't Cares Using Logic Implications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

An Analytical Study of People Mobility in Opportunistic Networks.

[BibT_eX]

[DOI]

Ling-Jyh Chen

J. Inf. Sci. Eng., 2010

Group detection in mobility traces.

[BibT_eX]

[DOI]

Proceedings of the 6th International Wireless Communications and Mobile Computing Conference, 2010

Node addition and removal in the presence of don't cares.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

2009

Dependent-Latch Identification in Reachable State Space.

[BibT_eX]

[DOI]

Chen-Hsuan Lin

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

A novel ACO-based pattern generation for peak power estimation in VLSI circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

An efficient approach to sip design integration.

[BibT_eX]

[DOI]

Meng-Syue Chan

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Fast detection of node mergers using logic implications.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Enhancing SAT-based sequential depth computation by pruning search space.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Novel Probabilistic Combinational Equivalence Checking.

[BibT_eX]

[DOI]

Shih-Chieh Wu

IEEE Trans. Very Large Scale Integr. Syst., 2008

An Implicit Approach to Minimizing Range-Equivalent Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

A Statistic-Based Approach to Testability Analysis.

[BibT_eX]

[DOI]

Chuang-Chi Chiou

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A Novel Mobility Model from a Heterogeneous Military MANET Trace.

[BibT_eX]

[DOI]

Proceedings of the Ad-hoc, Mobile and Wireless Networks, 7th International Conference, 2008

2007

Finding Self-Similarities in Opportunistic People Networks.

[BibT_eX]

[DOI]

Proceedings of the INFOCOM 2007. 26th IEEE International Conference on Computer Communications, 2007

2006

A hybrid routing approach for opportunistic networks.

[BibT_eX]

[DOI]

Proceedings of the 2006 SIGCOMM workshop on Challenged networks, 2006

Improving Bluetooth EDR Data Throughput Using FEC and Interleaving.

[BibT_eX]

[DOI]

Ling-Jyh Chen

Tony Sun

Proceedings of the Mobile Ad-hoc and Sensor Networks, Second International Conference, 2006

Language-Based High Level Transaction Extraction on On-chip Buses.

[BibT_eX]

[DOI]

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

An Improved Approach for AlternativeWires Identi.cation.

[BibT_eX]

[DOI]