Yung-Chi Chang

According to our database1, Yung-Chi Chang authored at least 23 papers between 1999 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
A 10b 400MS/s 2x-Time-Interleaved 2-Then-1b/Cycle SAR ADC in 90nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

2016
Opportunistic large array concentric routing algorithms with relay nodes for wireless sensor networks.
Comput. Electr. Eng., 2016

2014
A new hybrid architecture with an intersection-based coverage algorithm in wireless sensor networks.
Comput. Sci. Inf. Syst., 2014

2013
A Low-Energy Adaptive Clustering Hierarchy Architecture with an Intersection-Based Coverage Algorithm in Wireless Sensor Networks.
Proceedings of the Seventh International Conference on Innovative Mobile and Internet Services in Ubiquitous Computing, 2013

2011
Wafer defect inspection by neural analysis of region features.
J. Intell. Manuf., 2011

2009
Automatic Die Inspection for Post-sawing LED Wafers.
Proceedings of the IEEE International Conference on Systems, 2009

2007
Position Control of an Interior Permanent-Magnet Synchronous Motor Without Using a Shaft Position Sensor.
IEEE Trans. Ind. Electron., 2007

2006
Interactive Content-aware Video Streaming System with Fine Granularity Scalability.
J. VLSI Signal Process., 2006

Platform-Based MPEG-4 SOC Design for Video Communications.
J. VLSI Signal Process., 2006

2005
An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System.
J. VLSI Signal Process., 2005

Advances in Hardware Architectures for Image and Video Coding - A Survey.
Proc. IEEE, 2005

PEG, MPEG-4, and H.264 Codec IP Development.
Proceedings of the 2005 Design, 2005

2004
MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC.
Proceedings of the 4th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'04), 2004

2003
Hardware-oriented optimization and block-level architecture design for MPEG-4 FGS encoder.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Computationally controllable integer, half, and quarter-pel motion estimator for MPEG-4 Advanced Simple Profile.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Platform architecture design for MEG-4 video coding.
Proceedings of the 2003 International Conference on Image Processing, 2003

2002
VLSI architecture design of MPEG-4 shape coding.
IEEE Trans. Circuits Syst. Video Technol., 2002

Texture coder design of MPEG4 video by using interleaving schedule.
Proceedings of the 2002 IEEE International Conference on Multimedia and Expo, 2002

2001
Error-Propagation Analysis and Concealment Strategy for MPEG-4 Video Bitstream with Data Partitioning.
Proceedings of the 2001 IEEE International Conference on Multimedia and Expo, 2001

Design and implementation of JPEG encoder IP core.
Proceedings of ASP-DAC 2001, 2001

2000
MPEG-4 video bitstream structure analysis and its parsing architecture design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Performance analysis and architecture evaluation of MPEG-4 video codec system.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999
A VLSI architecture design of VLC encoder for high data rate video/image coding.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


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