Yung-Chen Chien

According to our database, Yung-Chen Chien authored at least 4 papers between 2011 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

A 0.2 V 32-Kb 10T SRAM With 41 nW Standby Power for IoT Applications.

Yung-Chen Chien, Jinn-Shyan Wang

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2017

ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures.

Po-Hao Wang, Yung-Chen Chien, Shang-Jen Tsai, Xuan-Yu Lin, Rizal Tanjung, Yi-Sian Lin, Shu-Wei Syu, Tay-Jyi Lin, Jinn-Shyan Wang, Tien-Fu Chen

IEEE Trans. Very Large Scale Integr. Syst., 2017

2015

A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs.

Jinn-Shyan Wang, Yung-Chen Chien, Fengzhi Liu, Pei-Yao Chang

IEEE Trans. Multi Scale Comput. Syst., 2015

2011

ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs.

Jinn-Shyan Wang, Yung-Chen Chien, Jia-Hong Lin, Chun-Yuan Cheng, Ying-Ting Ma, Chung-Hsun Huang

Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011