Yung-Chang Chang
Orcid: 0000-0003-4107-7787
According to our database1,
Yung-Chang Chang
authored at least 23 papers
between 2002 and 2020.
Collaborative distances:
Collaborative distances:
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On csauthors.net:
Bibliography
2020
J. Signal Process. Syst., 2020
21.3 A 5.69mm<sup>2</sup> 0.98nJ/Pixel Image-Processing SoC with 24b High-Dynamic-Range and Multiple Sensor Format Support for Automotive Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Filter-based deep-compression with global average pooling for convolutional networks.
J. Syst. Archit., 2019
A 0.7mm<sup>2</sup> 8.54mW FocusNet Display LSI for Power Reduction on OLED Smart-phones.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Filter-based Deep-Compression with Global Average Pooling for Convolutional Networks.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
2016
IEEE J. Solid State Circuits, 2016
A 2.6mm<sup>2</sup> 0.19nJ/pixel VP9 and multi-standard decoder LSI for Android 4K TV applications.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Energy and area efficient hardware implementation of 4K Main-10 HEVC decoder in Ultra-HD Blu-ray player and TV systems.
Proceedings of the 2015 IEEE International Conference on Multimedia and Expo, 2015
2014
Proceedings of the Symposium on VLSI Circuits, 2014
Assessing automotive functional safety microprocessor with ISO 26262 hardware requirements.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
A 0.2nJ/pixel 4K 60fps Main-10 HEVC decoder with multi-format capabilities for UHD-TV applications.
Proceedings of the ESSCIRC 2014, 2014
2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Area and Memory Efficient Architectures for 3D Blu-ray-compliant Multimedia Processors.
Proceedings of the 2012 IEEE International Conference on Multimedia and Expo, 2012
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Improvement of Multimedia Performance Based on 3-D Stacking Memory Architecture and Software Refinement.
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
Proceedings of the 14th IEEE International Conference on High Performance Computing and Communication & 9th IEEE International Conference on Embedded Software and Systems, 2012
2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
A packet-based emulating platform with serializer/deserializer interface for heterogeneous IP verification.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2007
J. Inf. Sci. Eng., 2007
2002
Modeling Frequently Accessed Wireless Data With Weak Consistency.
J. Inf. Sci. Eng., 2002