Yun-Chao Yu

According to our database, Yun-Chao Yu authored at least 3 papers between 2014 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

Hierarchical Test Integration Methodology for 3-D ICs.

Che-Wei Chou, Jin-Fu Li, Yun-Chao Yu, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou

IEEE Des. Test, 2015

A hybrid built-in self-test scheme for DRAMs.

Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Intra-channel Reconfigurable Interface for TSV and Micro Bump Fault Tolerance in 3-D RAMs.

Kuan-Te Wu, Jin-Fu Li, Yun-Chao Yu, Chih-Sheng Hou, Chi-Chun Yang, Ding-Ming Kwai, Yung-Fa Chou, Chih-Yen Lo

Proceedings of the 23rd IEEE Asian Test Symposium, 2014