Yumiko Iyama

According to our database, Yumiko Iyama authored at least 5 papers between 1990 and 1992.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

1992

Optimum redundancy design for new-generation EPROMs based on yield analysis of previous generation.

Ken-ichi Imamiya, Jun-ichi Miyamoto, Nobuaki Ohtuska, Naoto Tomita, Yumiko Iyama

Proceedings of the 10th IEEE VLSI Test Symposium (VTS'92), 1992

1991

A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique.

Naoto Tomita, Nobuaki Ohtsuka, Jun-ichi Miyamoto, Ken-ichi Imamiya, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Norihisa Arai, Yukio Kaneko, Eiji Sakagami, Kuniyoshi Yoshikawa, Sumio Tanaka

IEEE J. Solid State Circuits, November, 1991

Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme.

Jun-ichi Miyamoto, Nobuaki Ohtsuka, Ken-ichi Imamiya, Naoto Tomita, Yumiko Iyama

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990

A 16-ns 1-Mb CMOS EPROM.

Masao Kuriyama, Shigeru Atsumi, Ken-ichi Imamiya, Yumiko Iyama, Naohiro Matsukawa, Hitoshi Araki, Kazuhito Narita, Kazunori Masuda, Sumio Tanaka

IEEE J. Solid State Circuits, October, 1990

A 68-ns 4-Mbit CMOS EPROM with high-noise-immunity design.

Kenichi Imamiya, Jun-ichi Miyamoto, Shigeru Atsumi, Nobuaki Ohtsuka, Yukinori Muroya, Toshiyuki Sako, Masao Higashino, Yumiko Iyama, Seiichi Mori, Yoichi Ohshima, Hitoshi Araki, Yukio Kaneko, Kazuhito Narita, Norihisa Arai, Kuniyoshi Yoshikawa, Shinichi Tanaka

IEEE J. Solid State Circuits, February, 1990